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CMOS NAND, NOR (and NOT) circuits

Short answer

CMOS NAND uses parallel PMOS and series NMOS; output low only when both inputs high. NOR uses series PMOS and parallel NMOS; output high only when both inputs low. NOT (invert) has one PMOS and one NMOS; output is inverse of input.

Draw the MOS (CMOS) circuit diagrams for NAND, NOR and NOT gates, explain their operation and derive their truth tables.

CMOS gates use a pull-up network of PMOS transistors to VDD and a pull-down network of NMOS transistors to ground. A PMOS conducts when its gate is 0, an NMOS when its gate is 1. Exactly one network conducts for each input, so there is no static current.

NOT gate (inverter)

        VDD
         |
     |--+ PMOS
 A --|    |
     |--+-+------ Y
     |--+ |
 A --|    NMOS
     |--+
         |
        GND
  • A = 0: PMOS on, NMOS off, so Y = 1.
  • A = 1: PMOS off, NMOS on, so Y = 0.
AY
01
10

NAND gate

         VDD
       +--+--+
    P1 |     | P2        P1, P2 in parallel
 A -|<     B -|<
       +--+--+
          |
          +--------- Y
          |
       N1 | (A)       N1, N2 in series
          |
       N2 | (B)
          |
         GND

Y is pulled to 0 only when both NMOS are on (A = 1 and B = 1); otherwise at least one PMOS is on.

ABP1P2N1N2Y = (A·B)'
00ononoffoff1
01onoffoffon1
10offononoff1
11offoffonon0

NOR gate

         VDD
          |
       P1 | (A)       P1, P2 in series
          |
       P2 | (B)
          |
          +--------- Y
       +--+--+
    N1 |     | N2        N1, N2 in parallel
       +--+--+
         GND

Y is pulled to 1 only when both PMOS are on (A = 0 and B = 0); if any input is 1 an NMOS pulls Y to 0.

ABP1P2N1N2Y = (A+B)'
00ononoffoff1
01onoffoffon0
10offononoff0
11offoffonon0

✓ Answer checked by Claude Opus 5.5 (high effort)

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