TTL NOR gate; CMOS characteristics

TTL NOR gate

A TTL NOR gate (7402) uses a separate input transistor and phase splitter for each input, with the phase splitters in parallel, followed by a totem-pole output.

                 +5 V
   +-------+--------+----------+
 R1A 4k  R1B 4k   R2 1.6k    R4 130
   |       |        |          |
   b       b        +-----+    c
A--e Q1A B-e Q1B    |     +--b Q3
   c       c        |          e
   |       |     +--+--+       |
   |       |     c     c      D1
   +-------)---b Q2A   |       |
           +---------b Q2B     |
                 e     e       +--- Y
                 +--+--+       c
                    |     +--b Q4
                    +-----+    e
                    |          |
                  R3 1k        |
   GND -------------+----------+

(")" marks a crossing without connection.)

Circuit (standard 7402):

• Each input has its own input transistor (Q1A for A, Q1B for B) and its own phase splitter (Q2A, Q2B).
• Q2A and Q2B are connected in parallel: collectors joined (to R2 and Q3 base), emitters joined (to R3 and Q4 base).
• The output stage is the usual totem pole Q3, D1, Q4.

Operation:

• A = 0, B = 0: both Q1A and Q1B conduct through their emitters, so their bases are near 0.9 V. Q2A and Q2B get no base current and are OFF, so Q4 is OFF and Q3 is ON → Y = 1 (HIGH).
• A = 1 (B any): Q1A's emitter junction is reverse biased; its base current flows through the base–collector junction into Q2A, which saturates. Q2A alone pulls the common collector line low (Q3 OFF) and drives Q4 ON → Y = 0.
• B = 1 (A any): the same happens through Q1B and Q2B → Y = 0.

Hence $Y = \overline{A + B}$: because the phase splitters are in parallel, either input HIGH is enough to pull the output LOW.

CMOS characteristics

• Very low static power (nW per gate), since the PMOS and NMOS networks are never ON together; dynamic power $P_D = C_L V_{DD}^2 f$ rises with frequency.
• Wide supply range: 3–15 V for 4000B, 2–6 V for 74HC.
• High noise margin: about 30% of $V_{DD}$ (≈ 1.4 V at 5 V); output swings almost rail to rail (≈ 0 V to $V_{DD}$).
• High fan-out (about 50), as MOS inputs draw almost no current.
• Speed: 74HC about 8–10 ns delay (similar to LS TTL); 4000B slower (25–100 ns).
• Static sensitive: inputs must be protected and never left floating.