2-input TTL NAND; CMOS characteristics

2-input TTL NAND gate

              +5 V
   +-----------+----------+
   |           |          |
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
B--e     c--+  c          e
            +--b Q2       |
               e         D1
               |          |
               +-----+    +---- Y
               |     |    c
             R3 1k   +--b Q4
               |          e
   GND --------+----------+

(b, c, e = base, collector, emitter; Q1 is a multi-emitter transistor.)

Circuit parts (standard 7400):

• Q1 (multi-emitter input transistor): one emitter per input; works like an AND of diodes.
• Q2 (phase splitter): gives opposite signals at its collector and emitter to drive the output pair.
• Q3, D1, Q4 (totem-pole output): Q3 is the active pull-up, Q4 the pull-down; D1 makes sure Q3 stays OFF when Q4 is ON. R4 = 130 Ω limits the current spike while switching.

Operation:

• Any input LOW (≈ 0.2 V): that base–emitter junction of Q1 conducts, so Q1's base sits at about 0.2 + 0.7 = 0.9 V. This is too low to forward bias Q1's base–collector junction together with the base–emitter junctions of Q2 and Q4 (that needs about 3 × 0.7 = 2.1 V), so Q2 and Q4 are OFF. Q2's collector is pulled up through R2, so Q3 conducts as an emitter follower and the output is HIGH (typically about 3.4 V, at least 2.4 V guaranteed).
• All inputs HIGH: all emitter junctions of Q1 are reverse biased. Current from R1 flows through Q1's base–collector junction into the base of Q2 (Q1's base rises to about 2.1 V), so Q2 and Q4 saturate. The output is pulled LOW (about 0.2 V). Q2's collector is only about 0.9 V, which cannot forward bias both Q3's base–emitter junction and D1, so Q3 is OFF.

Hence $Y = \overline{AB}$.

CMOS characteristics

• Very low static power (nW per gate), since the PMOS and NMOS networks are never ON together; dynamic power $P_D = C_L V_{DD}^2 f$ rises with frequency.
• Wide supply range: 3–15 V for 4000B, 2–6 V for 74HC.
• High noise margin: about 30% of $V_{DD}$ (≈ 1.4 V at 5 V); output swings almost rail to rail (≈ 0 V to $V_{DD}$).
• High fan-out (about 50), as MOS inputs draw almost no current.
• Speed: 74HC about 8–10 ns delay (similar to LS TTL); 4000B slower (25–100 ns).
• Static sensitive: inputs must be protected and never left floating.