Propagation delay; 2-input TTL NAND

Propagation delay time

Propagation delay is the time a gate's output takes to respond to a change at its input, measured from the 50% point of the input edge to the 50% point of the output edge.

• $t_{PHL}$: input change to output going HIGH → LOW.
• $t_{PLH}$: input change to output going LOW → HIGH.
• Average: $t_{pd} = \dfrac{t_{PHL} + t_{PLH}}{2}$. For standard 7400 TTL, $t_{PLH} \approx 11$ ns and $t_{PHL} \approx 7$ ns, so $t_{pd} \approx 9$ ns.

 In   ____/--------\_______
          :         :
 Out  -----:-\_______:-/----
          |<>|      |<>|
          tPHL      tPLH

Smaller delay means a faster gate (higher maximum frequency).

2-input TTL NAND gate

A TTL NAND gate (7400) is built with bipolar transistors: a multi-emitter input transistor, a phase splitter and a totem-pole output.

              +5 V
   +-----------+----------+
   |           |          |
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
B--e     c--+  c          e
            +--b Q2       |
               e         D1
               |          |
               +-----+    +---- Y
               |     |    c
             R3 1k   +--b Q4
               |          e
   GND --------+----------+

(b, c, e = base, collector, emitter; Q1 is a multi-emitter transistor.)

Circuit parts (standard 7400):

• Q1 (multi-emitter input transistor): one emitter per input; works like an AND of diodes.
• Q2 (phase splitter): gives opposite signals at its collector and emitter to drive the output pair.
• Q3, D1, Q4 (totem-pole output): Q3 is the active pull-up, Q4 the pull-down; D1 makes sure Q3 stays OFF when Q4 is ON. R4 = 130 Ω limits the current spike while switching.

Operation:

• Any input LOW (≈ 0.2 V): that base–emitter junction of Q1 conducts, so Q1's base sits at about 0.2 + 0.7 = 0.9 V. This is too low to turn on the Q1 base–collector junction plus Q2 and Q4 (needs about 1.4 V), so Q2 and Q4 are OFF. Q2's collector is pulled up through R2, so Q3 conducts as an emitter follower and the output is HIGH (about 3.4 V with no load, at least 2.4 V guaranteed).
• All inputs HIGH: all emitter junctions of Q1 are reverse biased. Current from R1 flows through Q1's base–collector junction into the base of Q2, so Q2 and Q4 saturate. The output is pulled LOW (about 0.2 V). Q2's collector is only about 0.9 V, which cannot forward bias both Q3's base–emitter junction and D1, so Q3 is OFF.

Hence $Y = \overline{AB}$.