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2-input TTL NAND gate

Short answer

When any input is low, Q1's base sits at ~0.9V, Q2 and Q4 are off, Q3 on, output high (~3.4V). When both inputs are high, current through Q1's base-collector turns on Q2 and Q4, Q3 off, output low (~0.2V), giving Y = (AB)'. The totem-pole output ensures fast switching and fan-out of 10.

Draw 2-input TTL NAND gate and explain its working principle.

A TTL NAND gate (7400) is built with bipolar transistors: a multi-emitter input transistor, a phase splitter and a totem-pole output.

              +5 V
   +-----------+----------+
   |           |          |
 R1 4k      R2 1.6k    R4 130
   |           |          |
   b           +-----+    c
A--e  Q1       |     +--b Q3
B--e     c--+  c          e
            +--b Q2       |
               e         D1
               |          |
               +-----+    +---- Y
               |     |    c
             R3 1k   +--b Q4
               |          e
   GND --------+----------+

(b, c, e = base, collector, emitter; Q1 is a multi-emitter transistor.)

Circuit parts (standard 7400):

  • Q1 (multi-emitter input transistor): one emitter per input; works like an AND of diodes.
  • Q2 (phase splitter): gives opposite signals at its collector and emitter to drive the output pair.
  • Q3, D1, Q4 (totem-pole output): Q3 is the active pull-up, Q4 the pull-down; D1 makes sure Q3 stays OFF when Q4 is ON. R4 = 130 Ω limits the current spike while switching.

Operation:

  • Any input LOW (≈ 0.2 V): that base–emitter junction of Q1 conducts, so Q1's base sits at about 0.2 + 0.7 = 0.9 V. This is too low to forward bias Q1's base–collector junction together with the base–emitter junctions of Q2 and Q4 (that needs about 3 × 0.7 = 2.1 V), so Q2 and Q4 are OFF. Q2's collector is pulled up through R2, so Q3 conducts as an emitter follower and the output is HIGH (typically about 3.4 V, at least 2.4 V guaranteed).
  • All inputs HIGH: all emitter junctions of Q1 are reverse biased. Current from R1 flows through Q1's base–collector junction into the base of Q2 (Q1's base rises to about 2.1 V), so Q2 and Q4 saturate. The output is pulled LOW (about 0.2 V). Q2's collector is only about 0.9 V, which cannot forward bias both Q3's base–emitter junction and D1, so Q3 is OFF.
ABQ2, Q4Q3Y
00OFFON1
01OFFON1
10OFFON1
11ONOFF0

Hence Y=AB‾Y = \overline{AB}.

Key values: VOH≈3.4V_{OH} \approx 3.4 V (≥ 2.4 V), VOL≈0.2V_{OL} \approx 0.2 V (≤ 0.4 V), propagation delay ≈ 10 ns, power ≈ 10 mW per gate, fan-out 10.

✓ Answer checked by Claude Opus 5.5 (high effort)

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