CMOS parameters; 2-input CMOS NAND

CMOS parameters

The main parameters of a CMOS gate (typical 5 V values):

• Supply voltage $V_{DD}$: 3–15 V (4000B), 2–6 V (74HC).
• Input levels: $V_{IH(min)} \approx 3.5$ V (70% of $V_{DD}$), $V_{IL(max)} \approx 1.5$ V (30% of $V_{DD}$).
• Output levels: $V_{OH(min)} \approx 4.9$ V, $V_{OL(max)} \approx 0.1$ V (almost rail to rail).
• Noise margin: $NM_H = 4.9 - 3.5 = 1.4$ V, $NM_L = 1.5 - 0.1 = 1.4$ V.
• Power dissipation: nearly zero when static; dynamic $P_D = C_L V_{DD}^2 f$.
• Propagation delay: about 8–10 ns (74HC), 25–100 ns (4000B).
• Fan-out: about 50, limited by input capacitance, not by current.

2-input CMOS NAND gate

          VDD               VDD
           |                 |
    A --o| P1        B --o| P2
           |                 |
           +--------+--------+
                    |
                    +------------ Y = (AB)'
                    |
             A --| N1
                    |
             B --| N2
                    |
                   GND

(P = PMOS, ON when gate = 0; N = NMOS, ON when gate = 1.)

The two PMOS transistors are in parallel between $V_{DD}$ and the output; the two NMOS transistors are in series between the output and ground.

• A = 0 or B = 0: at least one PMOS is ON, connecting Y to $V_{DD}$, and the series NMOS path is broken → Y = 1.
• A = 1 and B = 1: both NMOS are ON, connecting Y to ground; both PMOS are OFF → Y = 0.

So $Y = \overline{AB}$. In no input state are both networks ON, so no DC current flows from $V_{DD}$ to ground.