CMOS NAND gate; totem-pole output

CMOS NAND gate

          VDD               VDD
           |                 |
    A --o| P1        B --o| P2
           |                 |
           +--------+--------+
                    |
                    +------------ Y = (AB)'
                    |
             A --| N1
                    |
             B --| N2
                    |
                   GND

(P = PMOS, ON when gate = 0; N = NMOS, ON when gate = 1.)

The two PMOS transistors are in parallel between $V_{DD}$ and the output; the two NMOS transistors are in series between the output and ground.

• A = 0 or B = 0: at least one PMOS is ON, connecting Y to $V_{DD}$, and the series NMOS path is broken → Y = 1.
• A = 1 and B = 1: both NMOS are ON, connecting Y to ground; both PMOS are OFF → Y = 0.

So $Y = \overline{AB}$. In no input state are both networks ON, so no DC current flows from $V_{DD}$ to ground.

Totem-pole output

Totem-pole output is the TTL output stage in which two transistors are stacked one above the other between $V_{CC}$ and ground, like a totem pole: Q3 (active pull-up) on top with R4 = 130 Ω and diode D1, and Q4 (pull-down) below. The output Y is taken from their junction. The phase splitter Q2 drives them in opposite phase, so only one is ON at a time.

   +5 V
    |
  R4 130
    |
    c
Q2c-b Q3   (ON for HIGH output)
    e
    |
   D1
    +------- Y
    c
Q2e-b Q4   (ON for LOW output)
    e
    |
   GND

Significance:

• Low output resistance in both states: Q3 sources current and Q4 sinks current, so load capacitance is charged and discharged quickly → short rise and fall times, higher speed than a resistor pull-up.
• Low power: in the LOW state Q3 is OFF, so no current flows from $V_{CC}$ through a pull-up into the ON transistor, unlike a passive (resistor) pull-up.
• D1 adds an extra 0.7 V drop so that Q3 stays OFF when Q4 is saturated.
• R4 limits the current spike that flows for a few ns when both transistors are briefly ON during switching.
• Limitation: totem-pole outputs must not be wired together (wired-AND); if one output is HIGH and another LOW, a large current flows and may damage the gates. Open-collector or tristate outputs are used for bus connections.