Thyristor gate triggering circuit

A gate triggering (firing) circuit produces the gate pulses that turn ON a thyristor at the required instant (firing angle $\alpha$). It must give enough gate current and voltage, a suitable pulse width, synchronism with the supply, and isolation between the low-voltage control and the high-voltage power circuit.

Requirements

• Gate current and voltage above $I_{gt}$, $V_{gt}$ but within the gate power limit.
• Pulse width long enough for the anode current to reach the latching current.
• Firing angle adjustable over the needed range and synchronised with the a.c. supply.
• No reverse gate voltage and no false pulses.

1. Resistance (R) triggering

  ~ ----+---- load ----+
        |              | A
        R1 (fixed)    SCR
        |              | K
        R2 (var) --D-- G
        |              |
  ~ ----+--------------+

The gate gets a fraction of the supply voltage. When it reaches $V_{gt}$ the SCR fires. Firing angle range is only $0^\circ$ to $90^\circ$; simple but sensitive to temperature and device spread.

2. RC triggering

Resistance-capacitance (RC) firing circuit (half wave):

      +------- load -------+
      |                    |
   ~ Vs                  A |
      |                  SCR
      |        R      D2   |K
      +---/\/\/\-----|>|-- G
      |     (variable)     |
      |   D1         C     |
      +---|<|---+---||-----+

1. In the negative half cycle the capacitor $C$ charges through $D_1$ to $-V_m$ (upper plate negative).
2. In the positive half cycle $C$ charges positively through the variable resistor $R$.
3. When the capacitor voltage reaches the gate trigger voltage $V_{gt}$ plus the drop of $D_2$, gate current flows and the SCR fires.
4. Increasing $R$ slows the charging, so firing is delayed. The firing angle can be varied from about $0^\circ$ to $180^\circ$ (an R-only circuit gives only $0^\circ$ to $90^\circ$). $D_2$ blocks reverse gate voltage.

3. UJT triggering

UJT relaxation oscillator firing circuit:

   +Vbb ----+-----------+
            |           |
            R          R2
            |           |
            +------- E  B2
            |     UJT
            C           B1
            |           |
   GND -----+          R1 ---> pulse to gate
                        |      (via pulse
   GND -----------------+       transformer)

1. The capacitor $C$ charges through $R$ from $V_{BB}$ with time constant $RC$.
2. When the capacitor voltage reaches the UJT peak point voltage $V_P = \eta V_{BB} + V_D$ ($\eta$ = intrinsic stand-off ratio), the emitter-$B_1$ path becomes conducting and $C$ discharges quickly through $R_1$.
3. The discharge produces a sharp voltage pulse across $R_1$, which is passed to the SCR gate through a pulse transformer.
4. When the capacitor voltage falls to the valley voltage, the UJT turns OFF and the cycle repeats. The pulse period is $T = RC \ln\frac{1}{1-\eta}$.
5. For a.c. circuits, $V_{BB}$ is obtained from the same supply through a rectifier and a Zener clamp, so the first pulse of every half cycle is synchronised with the supply; changing $R$ changes the firing angle.

The output pulses are given to the gate through a pulse transformer or opto-coupler, which provides isolation; a diode blocks negative gate voltage and a resistor across gate-cathode prevents noise triggering.