di/dt, dv/dt protection and gate circuit design

A thyristor must be protected against a high rate of rise of anode current ($di/dt$) at turn-on, and a high rate of rise of forward voltage ($dv/dt$) when it is OFF; the gate control circuit must also be designed to fire it reliably.

         Ls (di/dt)
   o----/\/\/\/----+-----------+
                   |           |
                 A |           Rs
                  SCR          |
                 K |           Cs
                   |           |
   o---------------+-----------+
       (RC snubber across SCR)

di/dt protection

di/dt protection (series inductor): when an SCR is turned ON, conduction starts in a small area near the gate and then spreads over the whole cathode area at about 0.1 mm/µs. If the anode current rises faster than this spreading, the current density in the small conducting area becomes very high, causing local hot spots and damage.

1. A small inductor $L_s$ is connected in series with the SCR. At turn-on the current can rise only at the rate

$$\frac{di}{dt} = \frac{V_s}{L_s}$$

so $L_s$ is chosen as $L_s \ge \frac{V_m}{(di/dt)_{rated}}$. 2. A strong gate pulse (high gate current with a fast rise) is also used, so that a larger area of the cathode turns ON at the start. 3. The snubber resistance $R_s$ limits the capacitor discharge current at turn-on, which is the other source of high $di/dt$.

dv/dt protection

dv/dt protection (RC snubber): when an SCR is in forward blocking, junction $J_2$ is reverse biased and behaves like a capacitor $C_j$. A fast-rising anode voltage drives a charging current $i = C_j\,\frac{dv}{dt}$ through the device. If this current is large enough it acts like a gate current and turns the SCR ON falsely. To prevent this, a series $R_s C_s$ snubber is connected across the SCR.

1. When a voltage step appears, the capacitor $C_s$ initially acts as a short circuit, so the voltage across the SCR cannot jump suddenly; it rises at the rate at which $C_s$ charges through the load and $R_s$.
2. With a series circuit inductance $L$, the rate is roughly $\frac{dv}{dt} \approx \frac{R_s V_s}{L}$, so $R_s$, $C_s$ (and $L$) are chosen to keep $dv/dt$ below the rated value.
3. $R_s$ limits the discharge current of $C_s$ through the SCR when it turns ON (the discharge current is about $V_s/R_s$), which protects against high $di/dt$ from the snubber itself. It also damps the $L$-$C_s$ oscillation. A diode across $R_s$ (polarised snubber) gives better dv/dt limiting while still limiting discharge current.

Factors in designing the gate control circuit

1. Gate current and voltage: must exceed $I_{gt}$ and $V_{gt}$ for all devices and temperatures, but stay within the gate characteristic limits ($V_{g,max}$, $I_{g,max}$, average and peak gate power).
2. Pulse width: long enough for the anode current to reach the latching current, especially with inductive loads; pulse trains are used for long conduction.
3. Rise time of gate current: a fast-rising, strong pulse turns on a larger area and improves di/dt capability.
4. Synchronisation and range: pulses must be locked to the supply and the firing angle adjustable over the required range.
5. Isolation: pulse transformer or opto-coupler between the control and power circuits.
6. No false triggering: a resistor (and capacitor) between gate and cathode, shielded leads, and no gate signal during reverse bias (a diode in series with the gate) to avoid extra leakage loss.
7. Gate power during reverse bias: gate pulse should be removed when the SCR is reverse biased.