Characteristics and specification of power electronic devices

A static switch is a switch with no moving parts. A power transistor works as a static switch by operating only in two states: cut-off (OFF, open switch) and saturation (ON, closed switch), and it is moved between them by its base current.

Transistor as a static switch

                 +Vcc
                  |
                 RL (load)
                  |
          Rb     C|  iC
   vB o--/\/\/---B|/
                  |\  NPN
                 E|
                  |
                 GND

• OFF state (cut-off): when $v_B \le 0$, $I_B = 0$, both junctions are reverse biased and $I_C \approx 0$ (only leakage). The transistor acts as an open switch and the full supply voltage $V_{CC}$ appears across C-E.
• ON state (saturation): when enough base current is supplied, both junctions are forward biased. $V_{CE(sat)}$ is only about 0.2 to 1 V, so the transistor acts as a closed switch and $I_C = \frac{V_{CC} - V_{CE(sat)}}{R_L}$.
• To be sure of saturation, the base current is made larger than the minimum value:

$$I_B > I_{BS} = \frac{I_{CS}}{\beta_{min}}, \qquad \text{ODF} = \frac{I_B}{I_{BS}}$$

where ODF (overdrive factor) is usually 1.5 to 3 (too much overdrive increases storage time).

• The active region is avoided because both $V_{CE}$ and $I_C$ are large there, giving high power loss $V_{CE} I_C$. In the switching mode the loss is small: in cut-off the current is nearly zero, and in saturation the voltage is nearly zero.

   iC
    ^ saturation
    | |     IB4
    | |----------------------
    | |     IB3
    | |----------------------  active
    | |     IB2               region
    | |----------------------
    | |     IB1
    | |----------------------
    |/_______________________  IB = 0
    +----------------------------> vCE
            cut-off region

The switch has no arcing, no wear, and can be operated at tens of kHz, which is why transistors are used in choppers, inverters and SMPS.

Generation of the base (gate) signal

The base signal is a train of pulses whose width and frequency are set by the control circuit (for example a PWM signal from a 555 timer, comparator or microcontroller). It is amplified and isolated before it reaches the base.

 +------------+   +-----------+   +--------+   +-------+
 | PWM / pulse|-->| isolation |-->| driver |-->| base  |
 | generator  |   | (opto or  |   | amp    |   | of    |
 | (555, uC)  |   | pulse tr.)|   | +/-V   |   | BJT   |
 +------------+   +-----------+   +--------+   +-------+

Base drive (gate signal) circuit: the base drive must (i) give a high base current quickly at turn-on, (ii) keep just enough base current to hold saturation during conduction, and (iii) pull out the stored charge with a negative base current at turn-off.

               C1
          +----||----+
   vin    |          |    R2
   o------+--/\/\/---+--/\/\/--> B
             R1                 (power
                                 BJT)
   GND -------------------------> E

1. Turn-on control: at the rising edge of $v_{in}$, capacitor $C_1$ acts as a short across $R_1$, so a large initial base current $I_{B1} \approx \frac{V_1 - V_{BE}}{R_2}$ flows and the BJT turns ON fast (short $t_d$ and $t_r$).
2. Conduction: $C_1$ charges and the base current settles to $I_B = \frac{V_1 - V_{BE}}{R_1 + R_2}$, which is just enough to keep the transistor in (near) saturation, so the storage time stays small.
3. Turn-off control: when $v_{in}$ goes to zero or negative, the charged $C_1$ forces a reverse base current $-I_{B2}$, which sweeps out the stored base charge quickly and reduces $t_s$ and $t_f$.

Other refinements: a Baker (anti-saturation) clamp diode from base to collector keeps the BJT just out of hard saturation; proportional base drive makes $I_B$ proportional to $I_C$; and an opto-coupler or pulse transformer isolates the logic circuit from the power circuit.

A thyristor must be protected against a fast rate of rise of anode current ($di/dt$) at turn-on and a fast rate of rise of forward voltage ($dv/dt$) while it is OFF. A series inductor gives di/dt protection and an RC snubber across the device gives dv/dt protection.

         Ls (di/dt)
   o----/\/\/\/----+-----------+
                   |           |
                 A |           Rs
                  SCR          |
                 K |           Cs
                   |           |
   o---------------+-----------+
       (RC snubber across SCR)

di/dt protection

di/dt protection (series inductor): when an SCR is turned ON, conduction starts in a small area near the gate and then spreads over the whole cathode area at about 0.1 mm/µs. If the anode current rises faster than this spreading, the current density in the small conducting area becomes very high, causing local hot spots and damage.

1. A small inductor $L_s$ is connected in series with the SCR. At turn-on the current can rise only at the rate

$$\frac{di}{dt} = \frac{V_s}{L_s}$$

so $L_s$ is chosen as $L_s \ge \frac{V_m}{(di/dt)_{rated}}$. 2. A strong gate pulse (high gate current with a fast rise) is also used, so that a larger area of the cathode turns ON at the start. 3. The snubber resistance $R_s$ limits the capacitor discharge current at turn-on, which is the other source of high $di/dt$.

 iA
  ^     without Ls (very steep)
  |    |  ____________
  |    | /  with Ls
  |    |/  .----------
  |    |  /  slope = Vs/Ls
  |    | /
 -+----+/--------------------> t
      gate pulse

dv/dt protection

dv/dt protection (RC snubber): when an SCR is in forward blocking, junction $J_2$ is reverse biased and behaves like a capacitor $C_j$. A fast-rising anode voltage drives a charging current $i = C_j\,\frac{dv}{dt}$ through the device. If this current is large enough it acts like a gate current and turns the SCR ON falsely. To prevent this, a series $R_s C_s$ snubber is connected across the SCR.

1. When a voltage step appears, the capacitor $C_s$ initially acts as a short circuit, so the voltage across the SCR cannot jump suddenly; it rises at the rate at which $C_s$ charges through the load and $R_s$.
2. With a series circuit inductance $L$, the rate is roughly $\frac{dv}{dt} \approx \frac{R_s V_s}{L}$, so $R_s$, $C_s$ (and $L$) are chosen to keep $dv/dt$ below the rated value.
3. $R_s$ limits the discharge current of $C_s$ through the SCR when it turns ON (the discharge current is about $V_s/R_s$), which protects against high $di/dt$ from the snubber itself. It also damps the $L$-$C_s$ oscillation. A diode across $R_s$ (polarised snubber) gives better dv/dt limiting while still limiting discharge current.

 v across SCR
   ^      without snubber
   |     ________________
   |    |      with snubber
   |    |   ___.---------
   |    | .'
   |    |/  slower rise
 --+----+--------------------> t
   step applied

Design note: with source voltage $V_s$, series inductance $L_s$ and snubber $R_s, C_s$, the usual relations are

$$\begin{aligned} \left(\frac{di}{dt}\right)_{max} &= \frac{V_s}{L_s}, & \left(\frac{dv}{dt}\right)_{max} &\approx \frac{R_s V_s}{L_s}, & R_s &\ge \frac{V_s}{I_{T(peak)}} \end{aligned}$$

so $L_s$ is fixed by the di/dt rating and $R_s$ then by the dv/dt rating.

A power transistor (BJT) is a three-layer, two-junction device (NPN or PNP) with a vertical structure suited to high voltage and current. Its V-I (output) characteristic is the graph of collector current $i_C$ against collector-emitter voltage $v_{CE}$ for different base currents $I_B$.

V-I characteristics

   iC
    ^ saturation
    | |     IB4
    | |----------------------
    | |     IB3
    | |----------------------  active
    | |     IB2               region
    | |----------------------
    | |     IB1
    | |----------------------
    |/_______________________  IB = 0
    +----------------------------> vCE
            cut-off region

• Cut-off region: $I_B = 0$; both junctions reverse biased; only a small leakage current $I_{CEO}$ flows. The transistor is OFF.
• Active region: base-emitter junction forward biased, collector-base reverse biased; $i_C = \beta I_B$. The device acts as an amplifier, but the power loss $v_{CE} i_C$ is large, so power circuits avoid this region.
• Saturation region: both junctions forward biased. $i_C$ is set by the external load and $v_{CE(sat)}$ is very small (0.2 to 1 V). The transistor is fully ON.
• Quasi-saturation: in power BJTs, the lightly doped collector drift region gives a region between active and hard saturation; operating here keeps storage time small.
• A primary breakdown ($BV_{CEO}$) and a second breakdown limit the safe operating area.

Use as a static switch

                 +Vcc
                  |
                 RL (load)
                  |
          Rb     C|  iC
   vB o--/\/\/---B|/
                  |\  NPN
                 E|
                  |
                 GND

• OFF state (cut-off): when $v_B \le 0$, $I_B = 0$, both junctions are reverse biased and $I_C \approx 0$ (only leakage). The transistor acts as an open switch and the full supply voltage $V_{CC}$ appears across C-E.
• ON state (saturation): when enough base current is supplied, both junctions are forward biased. $V_{CE(sat)}$ is only about 0.2 to 1 V, so the transistor acts as a closed switch and $I_C = \frac{V_{CC} - V_{CE(sat)}}{R_L}$.
• To be sure of saturation, the base current is made larger than the minimum value:

$$I_B > I_{BS} = \frac{I_{CS}}{\beta_{min}}, \qquad \text{ODF} = \frac{I_B}{I_{BS}}$$

where ODF (overdrive factor) is usually 1.5 to 3 (too much overdrive increases storage time).

• The active region is avoided because both $V_{CE}$ and $I_C$ are large there, giving high power loss $V_{CE} I_C$. In the switching mode the loss is small: in cut-off the current is nearly zero, and in saturation the voltage is nearly zero.

A thyristor (SCR) is a four-layer P-N-P-N, three-junction ($J_1, J_2, J_3$) semiconductor switch with three terminals: anode (A), cathode (K) and gate (G). It can be turned ON by a small gate pulse when forward biased, but once ON the gate loses control; it turns OFF only when its anode current falls below the holding current.

V-I characteristic

              IA
               ^
               |  |<- ON state (VT = 1-2 V)
               |  |
         IL ---|--|
         IH ---|--+.
               |    `.   Ig2 > Ig1 > Ig=0
               |      `-.___      ___
     -VBR      |            `----'   |
  -----+-------+---------------------+--> VAK
       |       |  forward blocking  VBO
       |       |  (leakage current)
       | reverse blocking
       | (leakage current)
       v reverse avalanche

1. Reverse blocking mode: cathode is positive with respect to anode. Junctions $J_1$ and $J_3$ are reverse biased and $J_2$ is forward biased, so only a small reverse leakage current flows. If the reverse voltage reaches the reverse breakdown voltage $V_{BR}$, avalanche breakdown occurs at $J_1$ and $J_3$; the current rises sharply and the device is usually destroyed.
2. Forward blocking mode: anode is positive and gate is open. $J_1$ and $J_3$ are forward biased but $J_2$ is reverse biased, so only a small forward leakage current flows. The SCR is OFF and blocks the forward voltage.
3. Forward conduction (ON) mode: if the forward voltage is raised to the forward breakover voltage $V_{BO}$ (with $I_g = 0$), junction $J_2$ breaks down by avalanche and the SCR switches suddenly to the ON state (the negative-resistance jump). The voltage across it drops to about 1 to 2 V and the current is limited only by the load. With gate current, $J_2$ breaks down at a lower voltage: the larger $I_g$, the smaller the breakover voltage ($I_{g2} > I_{g1}$). In practice the SCR is always turned ON by a gate pulse at a voltage well below $V_{BO}$.

Two important currents on the curve are the latching current $I_L$ (minimum current just after turn-on to stay ON) and the holding current $I_H$ (minimum current to remain ON); $I_L > I_H$.

Thyristor firing circuit

A firing (triggering) circuit supplies a gate pulse of correct magnitude, width and timing (firing angle $\alpha$) and is synchronised with the supply.

Resistance-capacitance (RC) firing circuit (half wave):

      +------- load -------+
      |                    |
   ~ Vs                  A |
      |                  SCR
      |        R      D2   |K
      +---/\/\/\-----|>|-- G
      |     (variable)     |
      |   D1         C     |
      +---|<|---+---||-----+

1. In the negative half cycle the capacitor $C$ charges through $D_1$ to $-V_m$ (upper plate negative).
2. In the positive half cycle $C$ charges positively through the variable resistor $R$.
3. When the capacitor voltage reaches the gate trigger voltage $V_{gt}$ plus the drop of $D_2$, gate current flows and the SCR fires.
4. Increasing $R$ slows the charging, so firing is delayed. The firing angle can be varied from about $0^\circ$ to $180^\circ$ (an R-only circuit gives only $0^\circ$ to $90^\circ$). $D_2$ blocks reverse gate voltage.

A UJT relaxation oscillator or a digital (microcontroller) circuit with a pulse transformer or opto-coupler is used when sharp pulses, wider range and isolation are needed.

A BJT is used as a switch in power circuits by driving it either fully OFF (cut-off) or fully ON (saturation) with its base current, never in the active region. In this way it behaves like an ideal ON/OFF switch with very small power loss.

Circuit and operation

                 +Vcc
                  |
                 RL (load)
                  |
          Rb     C|  iC
   vB o--/\/\/---B|/
                  |\  NPN
                 E|
                  |
                 GND

• OFF state (cut-off): when $v_B \le 0$, $I_B = 0$, both junctions are reverse biased and $I_C \approx 0$ (only leakage). The transistor acts as an open switch and the full supply voltage $V_{CC}$ appears across C-E.
• ON state (saturation): when enough base current is supplied, both junctions are forward biased. $V_{CE(sat)}$ is only about 0.2 to 1 V, so the transistor acts as a closed switch and $I_C = \frac{V_{CC} - V_{CE(sat)}}{R_L}$.
• To be sure of saturation, the base current is made larger than the minimum value:

$$I_B > I_{BS} = \frac{I_{CS}}{\beta_{min}}, \qquad \text{ODF} = \frac{I_B}{I_{BS}}$$

where ODF (overdrive factor) is usually 1.5 to 3 (too much overdrive increases storage time).

• The active region is avoided because both $V_{CE}$ and $I_C$ are large there, giving high power loss $V_{CE} I_C$. In the switching mode the loss is small: in cut-off the current is nearly zero, and in saturation the voltage is nearly zero.

   iC
    ^ saturation
    | |     IB4
    | |----------------------
    | |     IB3
    | |----------------------  active
    | |     IB2               region
    | |----------------------
    | |     IB1
    | |----------------------
    |/_______________________  IB = 0
    +----------------------------> vCE
            cut-off region

Switching waveforms and losses

 vB   ^ ____          ____
      ||    |        |    |
      |+    +--------+    +----
 vCE  ^     ______        ______
      |    |      |      |
 Vcc  |----'      |------'
 ~0.2 |           '__ON__
 iC   ^ ___        ___
      ||   |      |   |
      |'   '------'   '-----> t

• Conduction loss $= V_{CE(sat)} I_C \times$ duty ratio (small because $V_{CE(sat)}$ is small).
• Switching loss occurs during the short turn-on and turn-off intervals; it rises with frequency.

Example

For $V_{CC} = 200$ V, $R_L = 10\ \Omega$, $V_{CE(sat)} = 1$ V and $\beta_{min} = 20$: $I_{CS} = (200 - 1)/10 = 19.9$ A, $I_{BS} = 19.9/20 = 0.995$ A. With ODF = 2, the base drive is designed for about 2 A.

Points to note

• A freewheeling diode is connected across inductive loads to protect the BJT from voltage spikes at turn-off.
• A negative base current at turn-off reduces storage time.
• The BJT is a current-controlled device, so its driver must supply a continuous base current; for higher frequency a MOSFET or IGBT is often preferred.

A snubber circuit is a series resistor-capacitor ($R_s$-$C_s$) network connected across a thyristor to limit the rate of rise of forward voltage ($dv/dt$) across it and so prevent false turn-on.

Snubber circuit for an SCR

         Ls (di/dt)
   o----/\/\/\/----+-----------+
                   |           |
                 A |           Rs
                  SCR          |
                 K |           Cs
                   |           |
   o---------------+-----------+
       (RC snubber across SCR)

A polarised version places a diode $D_s$ in parallel with $R_s$: the capacitor charges through the diode (good dv/dt limiting) and discharges through $R_s$ (limited discharge current).

Why dv/dt protection is needed

In forward blocking, junction $J_2$ is reverse biased and acts like a capacitor $C_j$. A rapidly rising anode voltage causes a charging current

$$i_j = C_j\frac{dv}{dt}$$

to flow through $J_2$. This current acts like gate current. If it exceeds the triggering level, the SCR turns ON without any gate signal, which is a false (unwanted) turn-on.

How the snubber limits dv/dt

1. When a forward voltage step $V_s$ is applied across the OFF thyristor, the uncharged capacitor $C_s$ acts momentarily as a short circuit, so the anode voltage cannot jump instantly.
2. The capacitor charges through the load (and series inductance $L$) and $R_s$. The voltage across the SCR therefore rises at a controlled rate; with series inductance

$$\frac{dv}{dt} \approx \frac{R_s V_s}{L}$$

which is designed to be below the device's rated dv/dt. 3. When the SCR is later fired, $C_s$ discharges through it. $R_s$ limits this discharge current to about $V_s/R_s$, protecting the SCR from a high di/dt and peak current. 4. $R_s$ also damps the oscillation between the circuit inductance and $C_s$.

 v across SCR
   ^      without snubber
   |     ________________
   |    |      with snubber
   |    |   ___.---------
   |    | .'
   |    |/  slower rise
 --+----+--------------------> t
   step applied

The snubber values are a compromise: a larger $C_s$ gives better dv/dt protection but more loss ($\frac{1}{2}C_sV_s^2 f$ per cycle in $R_s$).

A thyristor is protected against high $dv/dt$ by an RC snubber connected across it and against high $di/dt$ by a small inductor in series with it.

dv/dt protection

• In forward blocking, junction $J_2$ acts like a capacitor; a fast rising voltage drives a current $C_j\,dv/dt$ that can falsely trigger the SCR.
• An $R_s$-$C_s$ snubber across the SCR makes the voltage rise slowly while $C_s$ charges ($dv/dt \approx R_s V_s/L$). $R_s$ limits the capacitor discharge current when the SCR turns ON.

di/dt protection

• At turn-on, conduction starts near the gate and spreads slowly; a very fast current rise creates hot spots.
• A series inductor $L_s$ limits $di/dt = V_s/L_s$. A strong, fast gate pulse also helps by turning ON a larger area at once.

         Ls (di/dt)
   o----/\/\/\/----+-----------+
                   |           |
                 A |           Rs
                  SCR          |
                 K |           Cs
                   |           |
   o---------------+-----------+
       (RC snubber across SCR)

Numerical: reverse recovery of a power diode

Given: $t_{rr} = 3.9\ \mu$s, $di/dt = 50$ A/µs, softness factor $S = t_b/t_a = 0.3$.

$$\begin{aligned} t_{rr} &= t_a + t_b = t_a(1 + S) \\ t_a &= \frac{3.9}{1.3} = 3.0\ \mu\text{s}, \qquad t_b = 0.3 \times 3 = 0.9\ \mu\text{s} \\ I_{RR} &= t_a\frac{di}{dt} = 3.0\ \mu\text{s} \times 50\ \text{A}/\mu\text{s} = 150\ \text{A} \\ Q_{RR} &= \tfrac{1}{2} I_{RR}\, t_{rr} = \tfrac{1}{2} \times 150 \times 3.9 \times 10^{-6} = 292.5\ \mu\text{C} \end{aligned}$$

Answer: $I_{RR} = 150$ A and $Q_{RR} = 292.5\ \mu$C.

Triac versus diac

A diac is a two-terminal, bidirectional trigger diode that conducts in either direction once its breakover voltage (about 30 V) is reached. A triac is a three-terminal bidirectional thyristor (two SCRs in anti-parallel with one gate) used to control a.c. power.

Example: in a fan regulator, the diac fires the triac when the RC network voltage reaches about 30 V.

Choosing between power BJT and power MOSFET

Key considerations for engineers:

1. Voltage level: at high voltage (above about 500 V), MOSFET $R_{DS(on)}$ is high, so conduction loss favours the BJT (or IGBT).
2. Switching frequency: at high frequency, switching loss dominates, so the MOSFET is chosen (SMPS, high-frequency converters).
3. Total loss: $P = P_{cond} + P_{sw}$, where $P_{sw} \propto f$; the device with lower total loss at the working current and frequency is chosen.
4. Drive circuit cost, ruggedness (safe operating area) and ease of paralleling.

Example: a 100 kHz, 48 V DC-DC converter uses a MOSFET; a low-frequency, high-voltage motor drive traditionally used BJTs (now usually IGBTs).

A thyristor (SCR) is a four-layer P-N-P-N, three-junction ($J_1, J_2, J_3$) semiconductor switch with three terminals: anode (A), cathode (K) and gate (G). It can be turned ON by a small gate pulse when forward biased, but once ON the gate loses control; it turns OFF only when its anode current falls below the holding current.

V-I characteristic

              IA
               ^
               |  |<- ON state (VT = 1-2 V)
               |  |
         IL ---|--|
         IH ---|--+.
               |    `.   Ig2 > Ig1 > Ig=0
               |      `-.___      ___
     -VBR      |            `----'   |
  -----+-------+---------------------+--> VAK
       |       |  forward blocking  VBO
       |       |  (leakage current)
       | reverse blocking
       | (leakage current)
       v reverse avalanche

1. Reverse blocking mode: cathode is positive with respect to anode. Junctions $J_1$ and $J_3$ are reverse biased and $J_2$ is forward biased, so only a small reverse leakage current flows. If the reverse voltage reaches the reverse breakdown voltage $V_{BR}$, avalanche breakdown occurs at $J_1$ and $J_3$; the current rises sharply and the device is usually destroyed.
2. Forward blocking mode: anode is positive and gate is open. $J_1$ and $J_3$ are forward biased but $J_2$ is reverse biased, so only a small forward leakage current flows. The SCR is OFF and blocks the forward voltage.
3. Forward conduction (ON) mode: if the forward voltage is raised to the forward breakover voltage $V_{BO}$ (with $I_g = 0$), junction $J_2$ breaks down by avalanche and the SCR switches suddenly to the ON state (the negative-resistance jump). The voltage across it drops to about 1 to 2 V and the current is limited only by the load. With gate current, $J_2$ breaks down at a lower voltage: the larger $I_g$, the smaller the breakover voltage ($I_{g2} > I_{g1}$). In practice the SCR is always turned ON by a gate pulse at a voltage well below $V_{BO}$.

Latching current versus holding current

• Latching current ($I_L$): the minimum anode current that must flow through the SCR immediately after it is triggered, while the gate pulse is still present, so that it stays ON after the gate pulse is removed. If the anode current has not reached $I_L$ when the gate pulse ends, the SCR turns OFF again.
• Holding current ($I_H$): the minimum anode current that must keep flowing to hold an already conducting SCR in the ON state (gate open). If the anode current falls below $I_H$, the SCR turns OFF and returns to forward blocking.
• $I_L$ is greater than $I_H$, usually $I_L \approx 2$ to $3\,I_H$. Example: for an SCR with $I_L = 40$ mA and $I_H = 15$ mA, the gate pulse must last until the anode current reaches 40 mA, but once ON it stays ON until the current drops below 15 mA.

Example: with an inductive load, current rises slowly, so a longer gate pulse (or a pulse train) is needed for the current to reach $I_L$.

A thyristor (SCR) is a four-layer P-N-P-N, three-junction ($J_1, J_2, J_3$) semiconductor switch with three terminals: anode (A), cathode (K) and gate (G). It can be turned ON by a small gate pulse when forward biased, but once ON the gate loses control; it turns OFF only when its anode current falls below the holding current.

V-I characteristic

              IA
               ^
               |  |<- ON state (VT = 1-2 V)
               |  |
         IL ---|--|
         IH ---|--+.
               |    `.   Ig2 > Ig1 > Ig=0
               |      `-.___      ___
     -VBR      |            `----'   |
  -----+-------+---------------------+--> VAK
       |       |  forward blocking  VBO
       |       |  (leakage current)
       | reverse blocking
       | (leakage current)
       v reverse avalanche

1. Reverse blocking mode: cathode is positive with respect to anode. Junctions $J_1$ and $J_3$ are reverse biased and $J_2$ is forward biased, so only a small reverse leakage current flows. If the reverse voltage reaches the reverse breakdown voltage $V_{BR}$, avalanche breakdown occurs at $J_1$ and $J_3$; the current rises sharply and the device is usually destroyed.
2. Forward blocking mode: anode is positive and gate is open. $J_1$ and $J_3$ are forward biased but $J_2$ is reverse biased, so only a small forward leakage current flows. The SCR is OFF and blocks the forward voltage.
3. Forward conduction (ON) mode: if the forward voltage is raised to the forward breakover voltage $V_{BO}$ (with $I_g = 0$), junction $J_2$ breaks down by avalanche and the SCR switches suddenly to the ON state (the negative-resistance jump). The voltage across it drops to about 1 to 2 V and the current is limited only by the load. With gate current, $J_2$ breaks down at a lower voltage: the larger $I_g$, the smaller the breakover voltage ($I_{g2} > I_{g1}$). In practice the SCR is always turned ON by a gate pulse at a voltage well below $V_{BO}$.

Holding and latching current

• Latching current ($I_L$): the minimum anode current that must flow through the SCR immediately after it is triggered, while the gate pulse is still present, so that it stays ON after the gate pulse is removed. If the anode current has not reached $I_L$ when the gate pulse ends, the SCR turns OFF again.
• Holding current ($I_H$): the minimum anode current that must keep flowing to hold an already conducting SCR in the ON state (gate open). If the anode current falls below $I_H$, the SCR turns OFF and returns to forward blocking.
• $I_L$ is greater than $I_H$, usually $I_L \approx 2$ to $3\,I_H$. Example: for an SCR with $I_L = 40$ mA and $I_H = 15$ mA, the gate pulse must last until the anode current reaches 40 mA, but once ON it stays ON until the current drops below 15 mA.

Why a vertical structure is used in power BJTs

      E        B        E
   ===[n+]=====[p]=====[n+]===
   ---------- p base ----------
   ------- n- drift region ----   (thick, lightly doped)
   ------- n+ substrate -------
              |
              C (bottom)

1. Large current area: current flows vertically through the whole chip area, so the cross-section is large and the current density and on-state resistance are low.
2. High voltage: the thick, lightly doped $n^-$ drift layer sits between base and collector and supports a high blocking voltage without making the chip large.
3. Better heat removal: the collector is the whole bottom of the chip, mounted on the heat sink.
4. Interdigitated emitter and base fingers on top reduce current crowding.

Commutation is the process of turning OFF a conducting thyristor by bringing its anode current below the holding current and applying reverse voltage for longer than its turn-off time.

Self commutation (load / resonant commutation)

   +Vs                 
    |     L      C
    +---[SCR]--LLLL--||---+
    |                     R (load)
    +---------------------+

The SCR is in series with an under-damped $L$-$C$ (and load $R$) circuit. When fired, the current is a damped sinusoid. After half a period the current tries to reverse and falls through zero; the SCR turns OFF by itself, and the charged capacitor applies reverse voltage across it. Used in series inverters and DC choppers.

 i  ^   .-.
    |  /   \
 ---+-'-----'-------> t
       SCR off at i = 0
 vC ^       ______
    |    .-'      (holds reverse
 ---+-.-'          voltage on SCR)

Line (natural) commutation

  ~ vs ---[SCR]---+
                  R
  ----------------+

In a.c. circuits the supply voltage reverses every half cycle. At the end of the positive half cycle the anode current falls to zero naturally and during the negative half cycle the SCR is reverse biased, so it turns OFF without any extra circuit. Used in controlled rectifiers, AC voltage controllers and cycloconverters.

 vs ^  .-.         .-.
    | /   \       /
 ---+-|----\-----/----> t
      a     \___/
 io ^  |\
    |  | \  current falls to 0
 ---+--+--\------------> t

Numerical: minimum gate pulse width

Given: $V = 10$ V, $R = 10\ \Omega$, $L = 10$ mH, $I_L = 200$ mA. For an RL circuit the current after firing is

$$i(t) = \frac{V}{R}\left(1 - e^{-tR/L}\right), \qquad \frac{V}{R} = 1\ \text{A}, \quad \frac{L}{R} = 1\ \text{ms}$$

The gate pulse must last until $i$ reaches $I_L$:

$$\begin{aligned} 0.2 &= 1\left(1 - e^{-t/10^{-3}}\right) \\ e^{-1000t} &= 0.8 \\ t &= -10^{-3}\ln(0.8) = 0.2231\ \text{ms} \end{aligned}$$

Answer: minimum gate pulse width $= 223.1\ \mu$s.

A power diode is a two-terminal P-N junction (with a lightly doped $n^-$ drift layer, the P-i-N structure) that conducts when its anode is positive with respect to the cathode and blocks when reverse biased. It is designed for large current and high reverse voltage.

Structure

   Anode
     |
   [ p+ ]   heavily doped
   [ n- ]   drift region (sets
   [    ]   reverse voltage rating)
   [ n+ ]   substrate
     |
   Cathode

V-I characteristic

              iD
               ^         /  forward
               |        /   conduction
               |       /
               |      /
     -VRRM     |    _/ slope 1/r
  ----+--------+---'--------------> vD
      |   reverse    Vcut-in
      |   leakage    (0.7-1 V)
      |   (very small)
      |
      v reverse breakdown (avalanche)

• Forward bias: after the cut-in voltage (about 0.7 to 1 V), the current rises rapidly. The forward drop at rated current is about 1 to 2 V because of the drift-region resistance (on-state resistance $r$).
• Reverse bias: only a small leakage current (µA to mA) flows until the reverse breakdown voltage $V_{BR}$. The diode is rated for a repetitive peak reverse voltage $V_{RRM}$ below this. Beyond breakdown, avalanche current flows and the diode may be damaged.

Reverse recovery characteristic

Reverse recovery: when a conducting diode is switched to reverse bias, its current does not stop at zero. The minority carriers stored in the junction must first be removed, so the current falls through zero, flows in the reverse direction for a short time and then decays to zero.

  iD
   ^ IF
   |-------.
   |        \  slope = di/dt
   |         \
 --+----------\--------------------> t
   |           \      .--------
   |            \   .'
   |   - IRR ....\.'   tb
   |          ta  |<->|
   |         |<-->|
   |         |<---trr--->|

• $t_a$: time from current zero to the peak reverse current $I_{RR}$, while charge stored in the depletion region is removed.
• $t_b$: time for the reverse current to decay from $I_{RR}$ to about $0.25 I_{RR}$, while charge in the bulk is removed.
• Reverse recovery time $t_{rr} = t_a + t_b$; softness factor $S = t_b / t_a$.
• Peak reverse current: $I_{RR} = t_a \dfrac{di}{dt}$.
• Reverse recovery (stored) charge $Q_{RR}$ is the area under the reverse current, approximately a triangle:

$$Q_{RR} = \tfrac{1}{2} I_{RR}\, t_{rr}$$

Depending on $S$, diodes are soft recovery ($S \approx 1$, less oscillation) or fast/abrupt recovery (small $S$). Reverse recovery causes extra switching loss and voltage spikes, so fast-recovery diodes are used in choppers and inverters.

A gate triggering (firing) circuit produces the gate pulses that turn ON a thyristor at the required instant (firing angle $\alpha$). It must give enough gate current and voltage, a suitable pulse width, synchronism with the supply, and isolation between the low-voltage control and the high-voltage power circuit.

Requirements

• Gate current and voltage above $I_{gt}$, $V_{gt}$ but within the gate power limit.
• Pulse width long enough for the anode current to reach the latching current.
• Firing angle adjustable over the needed range and synchronised with the a.c. supply.
• No reverse gate voltage and no false pulses.

1. Resistance (R) triggering

  ~ ----+---- load ----+
        |              | A
        R1 (fixed)    SCR
        |              | K
        R2 (var) --D-- G
        |              |
  ~ ----+--------------+

The gate gets a fraction of the supply voltage. When it reaches $V_{gt}$ the SCR fires. Firing angle range is only $0^\circ$ to $90^\circ$; simple but sensitive to temperature and device spread.

2. RC triggering

Resistance-capacitance (RC) firing circuit (half wave):

      +------- load -------+
      |                    |
   ~ Vs                  A |
      |                  SCR
      |        R      D2   |K
      +---/\/\/\-----|>|-- G
      |     (variable)     |
      |   D1         C     |
      +---|<|---+---||-----+

1. In the negative half cycle the capacitor $C$ charges through $D_1$ to $-V_m$ (upper plate negative).
2. In the positive half cycle $C$ charges positively through the variable resistor $R$.
3. When the capacitor voltage reaches the gate trigger voltage $V_{gt}$ plus the drop of $D_2$, gate current flows and the SCR fires.
4. Increasing $R$ slows the charging, so firing is delayed. The firing angle can be varied from about $0^\circ$ to $180^\circ$ (an R-only circuit gives only $0^\circ$ to $90^\circ$). $D_2$ blocks reverse gate voltage.

3. UJT triggering

UJT relaxation oscillator firing circuit:

   +Vbb ----+-----------+
            |           |
            R          R2
            |           |
            +------- E  B2
            |     UJT
            C           B1
            |           |
   GND -----+          R1 ---> pulse to gate
                        |      (via pulse
   GND -----------------+       transformer)

1. The capacitor $C$ charges through $R$ from $V_{BB}$ with time constant $RC$.
2. When the capacitor voltage reaches the UJT peak point voltage $V_P = \eta V_{BB} + V_D$ ($\eta$ = intrinsic stand-off ratio), the emitter-$B_1$ path becomes conducting and $C$ discharges quickly through $R_1$.
3. The discharge produces a sharp voltage pulse across $R_1$, which is passed to the SCR gate through a pulse transformer.
4. When the capacitor voltage falls to the valley voltage, the UJT turns OFF and the cycle repeats. The pulse period is $T = RC \ln\frac{1}{1-\eta}$.
5. For a.c. circuits, $V_{BB}$ is obtained from the same supply through a rectifier and a Zener clamp, so the first pulse of every half cycle is synchronised with the supply; changing $R$ changes the firing angle.

The output pulses are given to the gate through a pulse transformer or opto-coupler, which provides isolation; a diode blocks negative gate voltage and a resistor across gate-cathode prevents noise triggering.

Commutation is the process of turning OFF a conducting thyristor. The anode current is reduced below the holding current and a reverse voltage is kept across the device for longer than its turn-off time $t_q$, so that it regains its forward blocking ability.

Natural (line) commutation

  vs ~ ---[SCR]---+
                  |
                  R (load)
                  |
  ----------------+

In an a.c. circuit, the supply voltage passes through zero and reverses every half cycle. The load current falls to zero and the SCR is reverse biased by the supply itself, so it turns OFF without any extra components. Examples: phase-controlled rectifiers, AC voltage controllers, cycloconverters.

Forced commutation

        +---- C ------[TA]---+
        |  (-   +)           |
 +Vdc --+--------[T1]--------+--- load ---+
                                          |
 GND -------------------------------------+

When the auxiliary SCR $T_A$ is fired, the pre-charged capacitor $C$ is placed across $T_1$ with reverse polarity, forcing its current to zero and reverse biasing it.

In d.c. circuits the current never reaches zero naturally, so an external commutation circuit (usually a charged capacitor and an inductor, switched by an auxiliary thyristor $T_A$) forces the current to zero or applies reverse voltage. Classes:

• Class A (self/load commutation by resonant LC load)
• Class B (resonant pulse, LC across SCR)
• Class C (complementary, two SCRs with a capacitor)
• Class D (auxiliary SCR, impulse commutation)
• Class E (external pulse source)

Examples: DC choppers and inverters.

Comparison

The switching characteristics of a BJT show how its collector current and voltage change with time when the base drive is switched ON and OFF. Because of junction capacitances and charge stored in the base, the transistor needs a finite turn-on time and turn-off time.

Switching characteristics

Switching characteristics: when a base pulse is applied and removed, the collector current does not follow it at once, because of the junction capacitances and the stored charge in the base.

 iB  ^  IB1 _____________
     |     |             |
     |-----+             +-----------
     |                    |___ -IB2
 iC  ^          ___________
     |        /|           |\
     |      /  |           |  \
     |-----'   |           |   `----
     |<td>|<tr>|           |<ts>|<tf>|
           ton                 toff

• Delay time $t_d$: time for the input capacitance of the base-emitter junction to charge to about 0.7 V; $i_C$ rises from 0 to 10% of $I_{CS}$.
• Rise time $t_r$: $i_C$ rises from 10% to 90%. $t_{on} = t_d + t_r$.
• Storage time $t_s$: after the base drive is removed or reversed, the excess carriers stored in the base (saturation) must be removed before $i_C$ can fall. It is the longest interval and depends on the overdrive.
• Fall time $t_f$: $i_C$ falls from 90% to 10%. $t_{off} = t_s + t_f$.

Switching losses occur during $t_r$ and $t_f$, when both voltage and current are large. They rise with switching frequency.

Base (gate) signal generating circuit

 +---------+   +-----------+   +---------+    +---------+
 | 555 or  |-->| opto-     |-->| totem   |--->| base of |
 | uC PWM  |   | coupler   |   | pole    | Rb | power   |
 | (logic) |   | isolation |   | driver  |    | BJT     |
 +---------+   +-----------+   +---------+    +---------+
                                 +V / -V
                                 supply

1. A PWM or pulse generator (555 timer, comparator or microcontroller) sets the ON time and frequency.
2. An opto-coupler (or pulse transformer) isolates the logic circuit from the power circuit, whose emitter may float at high voltage.
3. A totem-pole (push-pull) driver with a $+V$ and $-V$ supply amplifies the signal: the upper transistor supplies forward base current $+I_{B1}$ to turn ON quickly; the lower transistor pulls a negative current $-I_{B2}$ from the base to remove stored charge and turn OFF quickly.
4. A speed-up capacitor across $R_b$ gives a high initial base current and a negative spike at turn-off; a Baker clamp diode avoids deep saturation, reducing storage time.

Reverse recovery: when a conducting diode is switched to reverse bias, its current does not stop at zero. The minority carriers stored in the junction must first be removed, so the current falls through zero, flows in the reverse direction for a short time and then decays to zero.

  iD
   ^ IF
   |-------.
   |        \  slope = di/dt
   |         \
 --+----------\--------------------> t
   |           \      .--------
   |            \   .'
   |   - IRR ....\.'   tb
   |          ta  |<->|
   |         |<-->|
   |         |<---trr--->|

• $t_a$: time from current zero to the peak reverse current $I_{RR}$, while charge stored in the depletion region is removed.
• $t_b$: time for the reverse current to decay from $I_{RR}$ to about $0.25 I_{RR}$, while charge in the bulk is removed.
• Reverse recovery time $t_{rr} = t_a + t_b$; softness factor $S = t_b / t_a$.
• Peak reverse current: $I_{RR} = t_a \dfrac{di}{dt}$.
• Reverse recovery (stored) charge $Q_{RR}$ is the area under the reverse current, approximately a triangle:

$$Q_{RR} = \tfrac{1}{2} I_{RR}\, t_{rr}$$

Numerical

Given: $t_{rr} = 3\ \mu$s, $di/dt = 30$ A/µs. No softness factor is given, so the usual assumption of abrupt recovery ($t_b \ll t_a$, so $t_{rr} \approx t_a$) is used.

$$\begin{aligned} Q_{RR} &= \tfrac{1}{2}\frac{di}{dt}\, t_{rr}^2 = \tfrac{1}{2} \times 30 \times 10^{6} \times (3 \times 10^{-6})^2 \\ &= 135 \times 10^{-6}\ \text{C} = 135\ \mu\text{C} \\ I_{RR} &= \sqrt{2 Q_{RR}\frac{di}{dt}} = \sqrt{2 \times 135 \times 10^{-6} \times 30 \times 10^{6}} \\ &= \sqrt{8100} = 90\ \text{A} \end{aligned}$$

(Check: $I_{RR} = t_{rr}\,di/dt = 3 \times 30 = 90$ A.)

Answer: stored charge $Q_{RR} = 135\ \mu$C, peak reverse current $I_{RR} = 90$ A.

The thyristor (SCR) is a four-layer PNPN device with anode A, cathode K and gate G. Its V-I characteristic shows anode current $I_A$ against anode-cathode voltage $V_{AK}$.

  Symbol          Structure
                     A
     A               |
     |             +---+
    _V_            | P |
     |\            +---+ J1
     | \ G         | N |
     K             +---+ J2
                   | P |---- G
                   +---+ J3
                   | N |
                   +---+
                     |
                     K

              IA
               ^
               |  |<- ON state (VT = 1-2 V)
               |  |
         IL ---|--|
         IH ---|--+.
               |    `.   Ig2 > Ig1 > Ig=0
               |      `-.___      ___
     -VBR      |            `----'   |
  -----+-------+---------------------+--> VAK
       |       |  forward blocking  VBO
       |       |  (leakage current)
       | reverse blocking
       | (leakage current)
       v reverse avalanche

• Avalanche (reverse) breakdown: in reverse bias, $J_1$ and $J_3$ block. When the reverse voltage reaches the reverse breakdown voltage $V_{BR}$, carriers gain enough energy to knock out more carriers (avalanche multiplication), and the reverse current rises sharply. This normally destroys the device, so it is operated below $V_{RRM}$.
• Forward breakover voltage $V_{BO}$: in forward bias with gate open, $J_2$ blocks. $V_{BO}$ is the forward voltage at which $J_2$ breaks down by avalanche and the SCR switches from forward blocking to the ON state without any gate signal. With gate current, the breakover voltage becomes smaller.

A power transistor does not switch instantly. Its switching characteristics describe the delay and transition times of collector current when base drive is applied and removed; a good base drive circuit shortens these times.

Switching characteristics

Switching characteristics: when a base pulse is applied and removed, the collector current does not follow it at once, because of the junction capacitances and the stored charge in the base.

 iB  ^  IB1 _____________
     |     |             |
     |-----+             +-----------
     |                    |___ -IB2
 iC  ^          ___________
     |        /|           |\
     |      /  |           |  \
     |-----'   |           |   `----
     |<td>|<tr>|           |<ts>|<tf>|
           ton                 toff

• Delay time $t_d$: time for the input capacitance of the base-emitter junction to charge to about 0.7 V; $i_C$ rises from 0 to 10% of $I_{CS}$.
• Rise time $t_r$: $i_C$ rises from 10% to 90%. $t_{on} = t_d + t_r$.
• Storage time $t_s$: after the base drive is removed or reversed, the excess carriers stored in the base (saturation) must be removed before $i_C$ can fall. It is the longest interval and depends on the overdrive.
• Fall time $t_f$: $i_C$ falls from 90% to 10%. $t_{off} = t_s + t_f$.

Switching losses occur during $t_r$ and $t_f$, when both voltage and current are large. They rise with switching frequency.

Turn-on and turn-off control by base drive

Base drive (gate signal) circuit: the base drive must (i) give a high base current quickly at turn-on, (ii) keep just enough base current to hold saturation during conduction, and (iii) pull out the stored charge with a negative base current at turn-off.

               C1
          +----||----+
   vin    |          |    R2
   o------+--/\/\/---+--/\/\/--> B
             R1                 (power
                                 BJT)
   GND -------------------------> E

1. Turn-on control: at the rising edge of $v_{in}$, capacitor $C_1$ acts as a short across $R_1$, so a large initial base current $I_{B1} \approx \frac{V_1 - V_{BE}}{R_2}$ flows and the BJT turns ON fast (short $t_d$ and $t_r$).
2. Conduction: $C_1$ charges and the base current settles to $I_B = \frac{V_1 - V_{BE}}{R_1 + R_2}$, which is just enough to keep the transistor in (near) saturation, so the storage time stays small.
3. Turn-off control: when $v_{in}$ goes to zero or negative, the charged $C_1$ forces a reverse base current $-I_{B2}$, which sweeps out the stored base charge quickly and reduces $t_s$ and $t_f$.

Other refinements: a Baker (anti-saturation) clamp diode from base to collector keeps the BJT just out of hard saturation; proportional base drive makes $I_B$ proportional to $I_C$; and an opto-coupler or pulse transformer isolates the logic circuit from the power circuit.

A transistor acts as a static switch (no moving parts) when it is operated only in cut-off (OFF) and saturation (ON), switched by its base current.

Transistor as a static switch

                 +Vcc
                  |
                 RL (load)
                  |
          Rb     C|  iC
   vB o--/\/\/---B|/
                  |\  NPN
                 E|
                  |
                 GND

• OFF state (cut-off): when $v_B \le 0$, $I_B = 0$, both junctions are reverse biased and $I_C \approx 0$ (only leakage). The transistor acts as an open switch and the full supply voltage $V_{CC}$ appears across C-E.
• ON state (saturation): when enough base current is supplied, both junctions are forward biased. $V_{CE(sat)}$ is only about 0.2 to 1 V, so the transistor acts as a closed switch and $I_C = \frac{V_{CC} - V_{CE(sat)}}{R_L}$.
• To be sure of saturation, the base current is made larger than the minimum value:

$$I_B > I_{BS} = \frac{I_{CS}}{\beta_{min}}, \qquad \text{ODF} = \frac{I_B}{I_{BS}}$$

where ODF (overdrive factor) is usually 1.5 to 3 (too much overdrive increases storage time).

• The active region is avoided because both $V_{CE}$ and $I_C$ are large there, giving high power loss $V_{CE} I_C$. In the switching mode the loss is small: in cut-off the current is nearly zero, and in saturation the voltage is nearly zero.

Base current signal generating circuit using an opto-coupler

 control side      |          power side
 +--------+        |         +--------------+
 | pulse  |  LED   | photo-  | totem pole   |-Rb-> B
 | (PWM)  |--|>~~~~~~> tran- | Q1 to +Vaux  |   (power
 +--------+        |  sistor | Q2 to -Vaux  |    BJT)
                   |         +--------------+---> E
     only light crosses the isolation barrier

1. The control pulse (PWM from a 555 timer or microcontroller) lights the LED of the opto-coupler through $R_1$.
2. The phototransistor turns ON and drives the totem-pole stage $Q_1$-$Q_2$, which is powered by an isolated auxiliary supply referenced to the emitter of the power BJT.
3. When the pulse is high, $Q_1$ conducts and supplies positive base current $I_{B1}$ through $R_b$; the power transistor saturates.
4. When the pulse is low, $Q_2$ conducts and connects the base to $-V_{aux}$, giving a negative base current that removes stored charge and turns the power BJT OFF quickly.
5. Since the only link between the two sides is light, the logic circuit is fully isolated from the high-voltage power circuit.

Reverse recovery: when a conducting diode is switched to reverse bias, its current does not stop at zero. The minority carriers stored in the junction must first be removed, so the current falls through zero, flows in the reverse direction for a short time and then decays to zero.

  iD
   ^ IF
   |-------.
   |        \  slope = di/dt
   |         \
 --+----------\--------------------> t
   |           \      .--------
   |            \   .'
   |   - IRR ....\.'   tb
   |          ta  |<->|
   |         |<-->|
   |         |<---trr--->|

• $t_a$: time from current zero to the peak reverse current $I_{RR}$, while charge stored in the depletion region is removed.
• $t_b$: time for the reverse current to decay from $I_{RR}$ to about $0.25 I_{RR}$, while charge in the bulk is removed.
• Reverse recovery time $t_{rr} = t_a + t_b$; softness factor $S = t_b / t_a$.
• Peak reverse current: $I_{RR} = t_a \dfrac{di}{dt}$.
• Reverse recovery (stored) charge $Q_{RR}$ is the area under the reverse current, approximately a triangle:

$$Q_{RR} = \tfrac{1}{2} I_{RR}\, t_{rr}$$

Soft and abrupt recovery

Effects of reverse recovery

• Extra switching loss $\approx V_R Q_{RR} f$.
• Over-voltage spikes $L\,di/dt$ in stray inductances.
• In bridge circuits, the recovering diode draws a current spike through the incoming switch.

Hence power circuits use fast recovery or Schottky diodes, which have small $t_{rr}$ (a few µs down to ns).

A thyristor (SCR) is a four-layer P-N-P-N, three-junction ($J_1, J_2, J_3$) semiconductor switch with three terminals: anode (A), cathode (K) and gate (G). It can be turned ON by a small gate pulse when forward biased, but once ON the gate loses control; it turns OFF only when its anode current falls below the holding current.

V-I characteristic

              IA
               ^
               |  |<- ON state (VT = 1-2 V)
               |  |
         IL ---|--|
         IH ---|--+.
               |    `.   Ig2 > Ig1 > Ig=0
               |      `-.___      ___
     -VBR      |            `----'   |
  -----+-------+---------------------+--> VAK
       |       |  forward blocking  VBO
       |       |  (leakage current)
       | reverse blocking
       | (leakage current)
       v reverse avalanche

1. Reverse blocking mode: cathode is positive with respect to anode. Junctions $J_1$ and $J_3$ are reverse biased and $J_2$ is forward biased, so only a small reverse leakage current flows. If the reverse voltage reaches the reverse breakdown voltage $V_{BR}$, avalanche breakdown occurs at $J_1$ and $J_3$; the current rises sharply and the device is usually destroyed.
2. Forward blocking mode: anode is positive and gate is open. $J_1$ and $J_3$ are forward biased but $J_2$ is reverse biased, so only a small forward leakage current flows. The SCR is OFF and blocks the forward voltage.
3. Forward conduction (ON) mode: if the forward voltage is raised to the forward breakover voltage $V_{BO}$ (with $I_g = 0$), junction $J_2$ breaks down by avalanche and the SCR switches suddenly to the ON state (the negative-resistance jump). The voltage across it drops to about 1 to 2 V and the current is limited only by the load. With gate current, $J_2$ breaks down at a lower voltage: the larger $I_g$, the smaller the breakover voltage ($I_{g2} > I_{g1}$). In practice the SCR is always turned ON by a gate pulse at a voltage well below $V_{BO}$.

The latching current $I_L$ and holding current $I_H$ ($I_L > I_H$) are marked on the ON-state part of the curve.

Isolation of the gate circuit by an opto-coupler

Opto-coupler isolation: the gate signal generator (logic level, grounded to the control circuit) and the power circuit (hundreds of volts, cathode floating) must be electrically separated. An opto-coupler does this with light.

   control side     |      power side
                    |          + Vaux
    R1              |          |
 o--/\/\--+         |          R2
 pulse    |         |          |
         LED ~~~~>  |   photo-transistor
          |  light  |   (C top, E below)
 o--------+         |          |
 GND                |          +------> G
                    |          |
                    |          R3
                    |          |
                    |  Vaux(-) +------> K

1. The control pulse drives a current through the LED through resistor $R_1$.
2. The LED emits infrared light, which falls on the phototransistor (or photo-SCR) inside the same package.
3. The phototransistor turns ON and connects the auxiliary supply $V_{aux}$ (referenced to the cathode) through $R_2$ to the gate, giving gate current. $R_3$ prevents false triggering by noise.
4. When the pulse ends, the LED is dark, the phototransistor turns OFF and gate current stops.

There is no electrical path between the two sides, so the isolation can withstand a few kV, and noise from the power circuit does not reach the logic circuit.

Data: $v_s = \sqrt{2}\times 230 \sin 314t$, so $V_m = 325.27$ V, $\omega = 314$ rad/s; $L = 15$ mH, $R = 2\ \Omega$; snubber $R_s = 10\ \Omega$, $C_s = 0.15\ \mu$F.

(i) Maximum di/dt and dv/dt

The worst case is when the voltage applied to the circuit is at its peak $V_m$, with zero initial current and an uncharged snubber capacitor.

di/dt at turn-on: when the SCR is fired, at $t = 0^+$ the current is zero, so the whole voltage appears across $L$:

$$\left(\frac{di}{dt}\right)_{max} = \frac{V_m}{L} = \frac{325.27}{15 \times 10^{-3}} = 21685\ \text{A/s} = 0.0217\ \text{A}/\mu\text{s}$$

dv/dt while OFF: the SCR is OFF and the snubber is in series with $L$ and $R$:

$$V_m = L\frac{di}{dt} + (R + R_s)\,i + v_C$$

The voltage across the SCR is $v_T = R_s i + v_C$. At $t = 0^+$, $i = 0$ and $v_C = 0$, so

$$\begin{aligned} \frac{dv_T}{dt} &= R_s\frac{di}{dt} + \frac{i}{C_s} = R_s\frac{V_m}{L} \\ &= 10 \times \frac{325.27}{0.015} = 216846\ \text{V/s} \approx 0.217\ \text{V}/\mu\text{s} \end{aligned}$$

(The snubber discharge current through the SCR at turn-on is limited by $R_s$ to $V_m/R_s = 32.5$ A.)

(ii) Average and RMS current of the SCR at $\alpha = 90^\circ$

The circuit is a half-wave controlled rectifier with RL load.

$$\begin{aligned} X_L &= \omega L = 314 \times 0.015 = 4.71\ \Omega \\ Z &= \sqrt{2^2 + 4.71^2} = 5.117\ \Omega \\ \phi &= \tan^{-1}\frac{4.71}{2} = 66.99^\circ \end{aligned}$$

Load (= SCR) current for $\alpha \le \omega t \le \beta$:

$$i = \frac{V_m}{Z}\left[\sin(\omega t - \phi) - \sin(\alpha - \phi)\,e^{-(\omega t - \alpha)/\tan\phi}\right]$$

Setting $i(\beta) = 0$ and solving numerically gives the extinction angle $\beta = 239.58^\circ$.

Average current (from the average output voltage):

$$\begin{aligned} I_{avg} &= \frac{V_m}{2\pi R}(\cos\alpha - \cos\beta) \\ &= \frac{325.27}{2\pi \times 2}(\cos 90^\circ - \cos 239.58^\circ) = 13.11\ \text{A} \end{aligned}$$

RMS current, by integrating $i^2$ from $\alpha$ to $\beta$:

$$I_{rms} = \sqrt{\frac{1}{2\pi}\int_{\alpha}^{\beta} i^2\, d(\omega t)} = 22.47\ \text{A}$$

Answer: $(di/dt)_{max} = 21685$ A/s, $(dv/dt)_{max} \approx 2.17 \times 10^5$ V/s; SCR average current $= 13.11$ A and RMS current $= 22.47$ A at $\alpha = 90^\circ$ (the SCR should be rated above these values with a safety margin).

A thyristor is turned ON by making its anode current exceed the latching current while it is forward biased. The usual and best method is gate triggering; once ON, it can be turned OFF in a d.c. circuit only by forced commutation.

Methods of turn-on

1. Forward voltage triggering: raising $V_{AK}$ above $V_{BO}$ (not used; may damage the device).
2. Gate triggering: a positive gate pulse between gate and cathode (normal method).
3. dv/dt triggering: a fast rise of anode voltage drives a capacitive current through $J_2$ (unwanted).
4. Thermal triggering: high temperature raises leakage (unwanted).
5. Light triggering: light falling on the junction creates carriers (LASCR, used in HVDC).

Two-transistor analogy (gate turn-on mechanism): the PNPN structure is split into a PNP transistor $Q_1$ and an NPN transistor $Q_2$ connected so that the collector of each drives the base of the other.

          A
          |
        [Q1 pnp] E
          |  \
       B1 |   C1 ----+
          |          |
    +---- C2      B2 +----- G
    |  [Q2 npn]
    |     E
    |     |
    +-----K

With common-base gains $\alpha_1$, $\alpha_2$ and leakage currents $I_{CBO1}$, $I_{CBO2}$,

$$I_A = \frac{\alpha_2 I_g + I_{CBO1} + I_{CBO2}}{1 - (\alpha_1 + \alpha_2)}$$

When a gate current $I_g$ is injected, the emitter current of $Q_2$ rises, $\alpha_2$ increases, its collector current feeds the base of $Q_1$, whose collector current in turn feeds $Q_2$. This regenerative (positive feedback) action drives $\alpha_1 + \alpha_2 \to 1$, the anode current rises sharply and both transistors saturate: the SCR is latched ON. After that the gate can be removed.

Forced commutation techniques

In d.c. circuits the anode current never falls to zero by itself, so an external circuit (L, C and often an auxiliary thyristor) forces it to zero and reverse biases the SCR for longer than its turn-off time $t_q$.

 Class D (impulse) commutation
        +---- C ------[TA]---+
        |  (-   +)           |
 +Vdc --+--------[T1]--------+--- load ---+
                                          |
 GND -------------------------------------+

Firing $T_A$ places the charged capacitor across $T_1$ with reverse polarity; $T_1$'s current is diverted, it turns OFF, and the load current then charges $C$ until $T_A$ also turns OFF.