How is a CMOS inverter connected?

PMOS and NMOS in series between VDD and ground, gates joined as input, drains joined as output

Two NMOS in parallel with a resistor

PMOS and NMOS in parallel between VDD and output

PMOS and NMOS with separate gate inputs

When A = 0, what happens?

PMOS is ON (V_GS = -VDD), NMOS is OFF, so Y = 1

PMOS is OFF, NMOS is ON, so Y = 1

PMOS is ON, NMOS is ON, so Y = 0

When A = VDD, why is Y = 0?

NMOS has V_GS = VDD and turns ON, connecting Y to ground; PMOS has V_GS = 0 and is OFF

PMOS turns ON and connects Y to ground

Why is static power nearly zero?

One transistor is always OFF in steady state, so no DC path from VDD to ground

Both transistors are ON but have high resistance

2078 Kartik · 4 marks

CMOS inverter operation

Short answer

A CMOS inverter consists of a PMOS pull-up and NMOS pull-down with gates tied as input and drains as output. When input is low, the PMOS is on and NMOS off, pulling output to VDD; when input is high, the NMOS is on and PMOS off, giving 0 V. In either steady state one transistor is off, so static power is nearly zero.

Explain the operation of a CMOS inverter with a circuit diagram.

A CMOS inverter is the basic CMOS gate: one PMOS and one NMOS enhancement MOSFET in series between $V_{DD}$ and ground, with their gates joined as the input and their drains joined as the output.

          VDD
           |
           s
   +---o| Q1 (PMOS)
   |       d
 A-+       +-------- Y = A'
   |       d
   +----| Q2 (NMOS)
           s
           |
          GND

Operation

A = 0 (0 V): for the PMOS, $V_{GS} = -V_{DD}$ , so Q1 is ON; for the NMOS, $V_{GS} = 0$ , so Q2 is OFF. The output is connected to $V_{DD}$ through Q1's low ON resistance → Y = 1.
A = 1 ( $V_{DD}$ ): Q1 has $V_{GS} = 0$ → OFF; Q2 has $V_{GS} = V_{DD}$ → ON. The output is connected to ground → Y = 0.

A	Q1 (PMOS)	Q2 (NMOS)	Y
0	ON	OFF	1
1	OFF	ON	0

Features

In either steady state one transistor is OFF, so no DC current flows from $V_{DD}$ to ground: static power is almost zero. Current flows only briefly while switching and to charge the load capacitance ( $P_D = C_L V_{DD}^2 f$ ).
Output swings nearly from 0 to $V_{DD}$ ; the switching threshold is about $V_{DD}/2$ , giving a high noise margin.
Very high input resistance gives a large fan-out.

✓ Answer checked by Claude Opus 5.5 (high effort)

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CMOS inverter operation

Operation

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