Hazards in asynchronous design; 2-bit comparator

Role of hazards in asynchronous circuit design

A hazard is an unwanted momentary pulse (glitch) at a circuit output caused by unequal propagation delays along different paths when an input changes. Types: static-1 (output should stay 1 but dips to 0), static-0, and dynamic hazards; essential hazards come from feedback delays.

In asynchronous circuits there is no clock to wait until signals settle, and outputs are fed back as state variables. A glitch can therefore be taken as a real change and drive the circuit into a wrong stable state, causing malfunction. So hazards must be removed, e.g. by adding redundant (consensus) terms in the K-map so that every pair of adjacent 1s is covered by a common group, and by careful delay control.

Two-bit magnitude comparator

It compares $A = A_1A_0$ and $B = B_1B_0$ and gives three outputs: $G$ ($A > B$), $E$ ($A = B$) and $L$ ($A < B$).

Let $x_1 = A_1 \odot B_1$ and $x_0 = A_0 \odot B_0$ (bit-equal signals). Compare the MSBs first; only if they are equal, compare the LSBs:

$$\begin{aligned} E &= x_1 x_0 \\ G &= A_1B_1' + x_1A_0B_0' \\ L &= A_1'B_1 + x_1A_0'B_0 \end{aligned}$$

From K-maps the same functions in plain SOP are:

$$G = A_1B_1' + A_0B_1'B_0' + A_1A_0B_0', \quad L = A_1'B_1 + A_0'B_1B_0 + A_1'A_0'B_0$$

Partial truth table:

 A1,B1 --[XNOR]-- x1      A0,B0 --[XNOR]-- x0
 x1, x0 ------------------[AND]------------ E

 A1,B1' ---[AND]---+
 x1,A0,B0' [AND]---+------[OR]------------- G

 A1',B1 ---[AND]---+
 x1,A0',B0 [AND]---+------[OR]------------- L

Example: $A = 11$, $B = 10$: $x_1 = 1$, $A_0B_0' = 1$, so $G = 1$. All 16 input combinations were verified.