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TTL input and output signal levels

Short answer

Standard TTL with Vcc=5V defines output HIGH ≥ 2.4V, output LOW ≤ 0.4V; input HIGH ≥ 2.0V, input LOW ≤ 0.8V. Indeterminate region 0.8–2.0V must be avoided, providing 0.4V noise margins.

Define TTL IC Signal levels for Input and Output logic with example.

TTL signal levels are the guaranteed voltage ranges that a standard TTL (74xx) gate, with VCC=5 VV_{CC} = 5\ \text{V}, accepts at its input and produces at its output as logic 0 and logic 1.

ParameterMeaningValue
VOH(min)V_{OH(min)}lowest output HIGH2.4 V
VOL(max)V_{OL(max)}highest output LOW0.4 V
VIH(min)V_{IH(min)}lowest input accepted as HIGH2.0 V
VIL(max)V_{IL(max)}highest input accepted as LOW0.8 V
 Output side           Input side
 5.0 +-----+           5.0 +-----+
     | HIGH|               | HIGH|
 2.4 +-----+  ------>  2.0 +-----+
     | bad |               |indet|
 0.4 +-----+  ------>  0.8 +-----+
     | LOW |               | LOW |
 0   +-----+           0   +-----+

Input voltages between 0.8 V and 2.0 V are indeterminate and must be avoided. The difference between output and input limits gives the noise margin:

NMH=VOH(min)−VIH(min)=2.4−2.0=0.4 VNML=VIL(max)−VOL(max)=0.8−0.4=0.4 V\begin{aligned} NM_H &= V_{OH(min)} - V_{IH(min)} = 2.4 - 2.0 = 0.4\ \text{V} \\ NM_L &= V_{IL(max)} - V_{OL(max)} = 0.8 - 0.4 = 0.4\ \text{V} \end{aligned}

Example: a 7400 output at logic 0 is at most 0.4 V. Even if 0.3 V of noise is added on the wire, the next gate sees 0.7 V, which is still below 0.8 V and is read as logic 0.

✓ Answer checked by Claude Opus 5.5 (high effort)

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