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Compose 4K x 16 ROM using 1K x 8

Short answer

Use 8 modules. Width: two per row form 16 bits. Depth: A11,A10 to a 2-to-4 decoder selects one of four rows. A9..A0 to all. Data outputs share tri-state bus. Addresses: 000-3FFH to C00-FFFH. Result: 4K×16 ROM.

Compose 4K × 16 ROM using 1K × 8 ROMs.

Given: base module 1K x 8 ROM; required: 4K x 16 ROM. Number of modules = (depth ratio) x (width ratio) = 4 x 2 = 8.

Method

  • Width: the required word is 16 bits and each module gives 8 bits, so 2 modules are placed side by side (same address and enable); their data outputs are combined to form the full word.
  • Depth: 4 times as many words are needed, so 4 rows of modules are used. The two extra high-order address lines A11 and A10 go to a 2-to-4 decoder whose outputs enable one row at a time. The low-order 10 address lines (A9..A0) go to every module in parallel. The rows share the same data lines (tri-state outputs).
  • Total address lines = 10 + 2 = 12; total data lines = 16.

Block diagram

 Address bits: 12 lines
   A11 A10 --> [2-to-4 decoder] --> row enables E0..E3
   A9..A0 --> to every module (parallel)

 row 0: [M00] [M01]  <- E0
 row 1: [M10] [M11]  <- E1
 row 2: [M20] [M21]  <- E2
 row 3: [M30] [M31]  <- E3

 Data: M*0: D7..D0, M*1: D15..D8

Address ranges (row selected by the high bits)

A11 A10Row enabledAddress range
00Row 0 (E0)000-3FFH
01Row 1 (E1)400-7FFH
10Row 2 (E2)800-BFFH
11Row 3 (E3)C00-FFFH

In each row, ROM M0 gives the low byte D7..D0 and ROM M1 gives the high byte D15..D8.

✓ Answer checked by Claude Opus 5.5 (high effort)

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