- Asked 2/19
- 2075 Baisakh · 4 marks
Compose 1K x 8 ROMs into 4K x 8 ROM
Short answer
Use 4 1K×8 ROMs. A11,A10 feed a 2-to-4 decoder to select one row. A9..A0 connect to all modules in parallel. 8-bit data outputs share a tri-state bus. Result: 4K×8 ROM.
Compose 1K × 8 ROMs into a 4K × 8 ROM.
Given: base module 1K x 8 ROM; required: 4K x 8 ROM. Number of modules = (depth ratio) x (width ratio) = 4 x 1 = 4.
Method
- Width: the word width is unchanged (8 bits), so no width expansion is needed.
- Depth: 4 times as many words are needed, so 4 rows of modules are used. The two extra high-order address lines A11 and A10 go to a 2-to-4 decoder whose outputs enable one row at a time. The low-order 10 address lines (A9..A0) go to every module in parallel. The rows share the same data lines (tri-state outputs).
- Total address lines = 10 + 2 = 12; total data lines = 8.
Block diagram
Address bits: 12 lines
A11 A10 --> [2-to-4 decoder] --> row enables E0..E3
A9..A0 --> to every module (parallel)
row 0: [M00] <- E0
row 1: [M10] <- E1
row 2: [M20] <- E2
row 3: [M30] <- E3
Data: 8 lines (all rows share them)
Address ranges (row selected by the high bits)
| A11 A10 | Row enabled | Address range |
|---|---|---|
| 00 | Row 0 (E0) | 000-3FFH |
| 01 | Row 1 (E1) | 400-7FFH |
| 10 | Row 2 (E2) | 800-BFFH |
| 11 | Row 3 (E3) | C00-FFFH |
Each 1K x 8 ROM has 10 address lines (A9..A0) and 8 data lines.
✓ Answer checked by Claude Opus 5.5 (high effort)
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