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Memory capacity from range and interfacing

Short answer

ROM capacity: 2000H bytes = 8KB (0000H–1FFFH). RAM1 capacity: 2000H bytes = 8KB (2000H–3FFFH). Interface: decode A15–A13 with 74LS138 (C,B,A = A15,A14,A13, G1=+5V, G2B'=GND, G2A'=IO/M'), Y0' to ROM CE', Y1' to RAM CS'. Both 8KB chips use A12–A0, RD' to OE', WR' to WE' of RAM, common data bus.

Determine the capacity of devices in the following memory range.

RangeDevice
0000-1FFFROM
2000-3FFFRAM1
Design an interfacing circuit to interface above memory devices with 8085 microprocessor.

Capacity of the devices

Capacity = (end address − start address) + 1.

  • ROM: 1FFFH − 0000H + 1 = 2000H = 2¹³ = 8192 locations = 8K×8 (8 KB); it needs 13 address lines A12–A0.
  • RAM1: 3FFFH − 2000H + 1 = 2000H = 8192 locations = 8K×8 (8 KB); it also needs A12–A0.

Address decoding

DeviceRangeA15 A14 A13
ROM0000H – 1FFFH0 0 0
RAM12000H – 3FFFH0 0 1

A12–A0 vary inside each chip. Only A15, A14, A13 (and IO/M') are decoded.

Interfacing circuit (74LS138)

  • C, B, A = A15, A14, A13. 000 → Y0' (ROM); 001 → Y1' (RAM1).
  • G1 = +5 V, G2B' = GND, G2A' = IO/M' (memory cycle only).
  • Y0' → CE' of ROM; Y1' → CS' of RAM1.
  • A12–A0 → address pins of both chips.
  • RD' → OE' of ROM and RAM1; WR' → WE' of RAM1 only.
  • D7–D0 (AD7–AD0) connect to the data pins of both chips.
 A15 -- C \
 A14 -- B  | 74LS138     +--------+
 A13 -- A /   Y0' ------ |CE' ROM | 0000-1FFF
 IO/M' - G2A' Y1' --+    |8K x 8  |
 GND --- G2B'       |    +--------+
 +5V --- G1         |    +--------+
                    +----|CS' RAM1| 2000-3FFF
                         |8K x 8  |
 A12-A0 -> both;  RD'->OE';  WR'->WE' (RAM)

The lower address byte is multiplexed with data on AD7–AD0, so a 74LS373 latch enabled by ALE is first used to separate A7–A0. A15–A8 are available directly. Signals marked with a prime (RD', WR', IO/M', CE', OE') are active low.

✓ Answer checked by Claude Opus 5.5 (high effort)

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