- 2068 Bhadra · 2+6 marks
Unique/non-unique decoding, memory mapped I/O
Short answer
Unique decoding uses all address lines so each location has one address; non-unique decoding ignores some lines, causing mirror addresses and wasted space. Memory mapped I/O gives a device a memory address and uses memory instructions; for example, an output port at 8000H is written with STA 8000H.
What do you mean by unique and non-unique address decoding? Explain memory mapped I/O along with an example.
Unique and non-unique decoding
Address decoding is the process of generating a chip-select signal from the address lines so that a memory or I/O device responds only to its own addresses.
- Unique (absolute, full) decoding: all address lines (A0–A15 for a 16-bit address) are used, either to select the chip or inside the chip. Each device location responds to exactly one address. It needs more decoding hardware but wastes no address space.
- Non-unique (partial) decoding: some higher-order address lines are ignored (don't care). The same device responds to more than one address (a "foldback" or mirror image). The hardware is simpler and cheaper, but part of the address space is wasted, and the mirrored addresses cannot be given to any other device.
Example: an I/O port decoded with only A15 and A14 responds to every address whose A15A14 = 10, i.e. 8000H–BFFFH, so the decoding is non-unique.
Memory mapped I/O
In memory mapped I/O the I/O device is given a memory address and is accessed with memory instructions and the memory control signals MEMR/MEMW (IO/M = 0). All 16 address lines are decoded.
Example: an 8-bit output port (8-bit latch such as the 74LS373) at address 8000H on the 8085, with unique decoding:
A14..A0 -> [15-input NOR] -> X (1 when all are 0)
A15 ---------------------\
X -----------------------> [AND] -> SEL (address = 8000H)
IO/M' = 0 (memory cycle) and WR' = 0 -> MEMW active
LE (latch enable, active high) = AND(SEL, MEMW active)
OE' of the latch tied to ground (outputs always enabled)
D0-D7 -> [74LS373 latch] -> output port
Condition: A15 = 1, A14–A0 = 0, IO/M = 0, WR = 0 → latch enabled; the data on D0–D7 is latched to the port.
Program:
MVI A,55H ; data to output
STA 8000H ; write to the port (memory write cycle)
LDA 8000H ; read back only if an input port is also decoded at 8000H
Because the port is in the memory map, the address 8000H cannot be used by memory, and any memory-reference instruction (e.g. MOV M,A with HL = 8000H) can also access it.
✓ Answer checked by Claude Opus 5.5 (high effort)
Related questions
- Address decoding with PROM decoder · Microprocessor, chapter 4
- Address decoding for two 8 KB RAM at C000H · Microprocessor, chapter 4
- Short note: I/O mapped and memory mapped I/O · Microprocessor, chapter 4
- Address decoding for 8 LEDs output port · Microprocessor, chapter 4
- Address decoding for input and output ports · Microprocessor, chapter 4
- Address decoding for input port at 8050H · Microprocessor, chapter 4
- Unique vs non-unique address decoding · Instrumentation II, chapter 2
- Full vs partial address decoding for memory · Instrumentation II, chapter 2
- Memory-mapped I/O reduces address space · Computer Organization and Architecture, chapter 7
- Memory-mapped I/O design for 8085 · Instrumentation II, chapter 2