Interrupt pins of 8085

The 8085 has five hardware interrupt inputs (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) and one output INTA' for acknowledgement.

Use of each pin

• TRAP: used for serious events (power failure, bus error). It is not affected by DI or SIM masks. It must stay high until acknowledged, which avoids false triggering by noise.
• RST 7.5: a rising edge sets an internal flip-flop, so a short pulse is remembered until it is serviced. The flip-flop can be reset by the SIM instruction (R7.5 bit) and the request can be masked using M7.5.
• RST 6.5 and RST 5.5: level-sensitive, so the input must remain high until the 8085 samples it. They can be masked with the SIM instruction.
• INTR: a general-purpose interrupt, used with an external interrupt controller (8259). When it is accepted, the 8085 sends INTA'. The external hardware places an instruction (an RST n opcode, or CALL with an address) on the data bus, and the 8085 executes it. So the vector is chosen by the device.
• INTA': output. It tells the requesting device that INTR is accepted so the device can place the opcode on the bus. RST 7.5/6.5/5.5 and TRAP do not use INTA'; they have internal vectors.

All maskable interrupts are disabled by DI and by reset; EI enables them. When an interrupt is accepted, further maskable interrupts are disabled until EI is executed in the ISR.