What is the role of ALE in a machine cycle?

It goes high in T1 so an external latch can hold A7-A0 from AD7-AD0

It goes low in T2 to enable reading from memory

It stays high through the whole cycle while data is on the bus

It is an input from memory telling the CPU the address is latched

During the I/O write cycle of OUT 80H, what is the IO/M signal?

High, because an I/O port is addressed

Low, because the CPU is writing data

Low, because the port address is only 8 bits

It floats, because RD and WR choose the device

What happens if a slow memory keeps READY low when the CPU samples it?

The CPU inserts wait states until READY goes high, then continues the cycle

The CPU aborts the cycle and fetches the next instruction

The CPU raises a TRAP interrupt

The CPU reads whatever is on the data bus immediately

Why are AD0-AD7 called multiplexed lines?

They carry the low-order address A0-A7 during T1 and 8-bit data in the remaining T-states

They carry the high-order address A8-A15 and data at the same time

They are output-only lines shared between memory and I/O

They carry status signals S0 and S1 along with the data

2070 Bhadra · 5 marks

Uses of ALE, IO/M, READY, RD pins

Short answer

ALE latches the low address from AD7-AD0 during T1. IO/M selects I/O (high) or memory (low). READY inserts wait states when low. RD reads data from memory or I/O. AD0-AD7 carry the low address in T1 and data in other T-states.

Write the use of following pins of 8085 microprocessor. ALE, IO/M, READY, RD, AD0-AD7.

Pin	Use
ALE	Address Latch Enable, an output. It goes high during T1 of every machine cycle, which tells that AD7-AD0 carry the low-order address. An external latch (74LS373) uses it to hold the address, so the lines can then carry data.
IO/M	Output that separates memory and I/O operations. High means the I/O port is addressed (IN, OUT); low means memory is addressed. Combined with RD and WR it forms MEMR, MEMW, IOR and IOW control signals.
READY	Input used to interface slow memory or peripherals. The CPU samples it in T2; if it is low, the CPU inserts wait states (T-states without action) until the device is ready, then the cycle continues.
RD	Active-low output. Low shows the selected memory location or I/O port should place its data on the data bus, so the CPU reads it.
AD0-AD7	Multiplexed bidirectional lines. During T1 they carry the low-order address A0-A7; in the remaining T-states they carry the 8-bit data (input in read, output in write).

Example: in a memory read machine cycle, ALE = 1 in T1 with AD7-AD0 = A7-A0; ALE = 0 afterwards; IO/M = 0; RD goes low in T2-T3; the data is read on AD7-AD0 at the end of T3.

✓ Answer checked by Claude Opus 5.5 (high effort)

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