When an I/O device is much slower than the microprocessor or has unpredictable timing, what must be done?

The processor must synchronise with the device using polling, interrupt or DMA transfer

The device clock must be raised to the CPU speed

The CPU must stop and wait until the program ends

Data must be sent without any control signals

In 8255 mode 1 input handshake, what does IBF indicate?

The input buffer is full: data has been latched and the CPU can read it

The device has finished sending all data

The CPU has acknowledged an interrupt

Which is the correct order of signals in a DMA transfer?

DREQ from device, HOLD to CPU, HLDA from CPU, DACK to device

HLDA from CPU, DREQ, HOLD, DACK

HOLD from device, DACK from CPU, DREQ, HLDA

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Data transfer techniques for slow I/O

Short answer

When I/O speed mismatches, use: status check (polling with handshake, CPU wastes time), interrupt-driven transfer (device signals readiness via INTR, CPU performs ISR to transfer byte, allowing concurrency), or direct memory access (DMA controller takes bus control from CPU, transfers block directly between device and memory). DMA offers highest speed with lowest CPU load.

If the speeds of I/O devices do not match the speed of the microprocessor, what types of data transfer techniques are used? Describe them with necessary block diagrams and control signals.

When the I/O device is much slower than the microprocessor (or has an unpredictable timing), the processor must synchronise with it. The techniques are: (1) status check (polling) with handshake, (2) interrupt driven transfer, and (3) DMA.

1. Handshake / status check (programmed I/O)

The processor reads a status flag of the device repeatedly until it is ready, then transfers data. Control signals (for an input device with an 8255 in mode 1): STB' (strobe from device: data is valid), IBF (input buffer full: tells the device data is latched), and for output OBF' and ACK'.

 Device                 Port (8255)            CPU
   | --- data ---------> |                      |
   | --- STB'  --------> | IBF = 1 ------------>| polls status
   | <-- IBF   --------- |                      | IN data
   |                     | IBF = 0 (after RD')  |

Simple, but the CPU wastes time in the polling loop.

2. Interrupt driven transfer

The device raises an interrupt request (INTR/IRQ) when it is ready. The CPU completes the current instruction, saves the return address, and jumps to the service routine (via INTA' and vector), which transfers the byte and returns. The CPU does other work meanwhile.

 Device --INTR--> [Interrupt controller] --INT--> CPU
 CPU --INTA'--> controller (vector)      CPU <-> Data bus <-> Device

Signals: INTR/INT, INTA', RD', WR', IR0-IR7.

3. DMA (direct memory access)

For fast or block transfers, a DMA controller (8237) takes over the bus. The device sends DREQ, the controller sends HOLD to the CPU, the CPU answers HLDA and floats its buses, the controller issues DACK to the device, and generates address, MEMR'/IOW' (or MEMW'/IOR') for each byte until the count is over.

 Device --DREQ--> DMAC --HOLD--> CPU
 Device <--DACK-- DMAC <--HLDA-- CPU
 DMAC drives address bus, MEMR', MEMW', IOR', IOW'
 Data goes Device <-> Memory directly

Technique	CPU load	Speed	Hardware
Polling	Very high	Low	Very simple
Interrupt	Medium	Medium	Interrupt controller
DMA	Very low	Highest	DMA controller

✓ Answer checked by Claude Sonnet 5.5

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Data transfer techniques for slow I/O

1. Handshake / status check (programmed I/O)

2. Interrupt driven transfer

3. DMA (direct memory access)

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