Which pairing correctly contrasts error detection and error correction?

Detection only finds errors and uses retransmission (ARQ); correction fixes them at the receiver (FEC) without a return channel

Detection fixes errors with FEC; correction asks for retransmission

Detection needs more redundancy than correction

Both always need a return channel

In terms of dmin, how many errors can a code detect and correct?

Detect dmin-1, correct floor((dmin-1)/2)

Detect floor((dmin-1)/2), correct dmin-1

The rate-1/2 encoder designed has k = 1, n = 2, K = 3. What does this mean?

1 input bit gives 2 output bits, with 2 memory flip-flops and 4 states

2 input bits give 1 output bit, with 3 states

1 input bit gives 2 output bits, with 3 memory flip-flops and 8 states

1 input bit gives 1 output bit, with 4 states

2079 Chaitra · 2+4+4 marks

Error detection vs correction; rate ½ convolutional encoder

Short answer

Error detection identifies errors; error correction identifies and corrects them. For rate-1/2 convolutional encoder with generators 111 and 101, code tree and trellis diagram show outputs for each input bit and state transitions.

Differentiate error-detection and error-correction. Design a convolutional encoder having code-rate of ½. Also, draw the code-tree and trellis diagram for the same assuming any three-bit input.

Error detection vs error correction

Point	Error detection	Error correction
Aim	Only finds that an error occurred	Finds and fixes the error
Redundancy	Few check bits (parity, CRC)	More check bits
Action on error	Request retransmission (ARQ)	Corrected at receiver (FEC)
Capability	Detects $d_{min}-1$ errors	Corrects $\lfloor (d_{min}-1)/2\rfloor$
Return channel	Needed	Not needed
Examples	Parity, checksum, CRC	Hamming, BCH, convolutional

Rate-1/2 convolutional encoder (design)

Choose $k=1$ input bit, $n=2$ output bits ( $r=1/2$ ), constraint length $K=3$ (two memory flip-flops, 4 states) and generators $g^{(1)}=111$ , $g^{(2)}=101$ .

 Encoder: g1 = 111, g2 = 101 (K = 3, rate 1/2)

 m -->[ m_i ]-->[ m_i-1 ]-->[ m_i-2 ]
        |          |           |
        +---(+)----+-----------+---> c1 = mi+mi-1+mi-2
        |                      |
        +---(+)----------------+---> c2 = mi+mi-2
            output per bit: c1 c2

A commutator samples $c_1$ then $c_2$ for each input bit, so two bits go out for every bit in.

State = previous two inputs $(m_{i-1}m_{i-2})$ : a = 00, b = 10, c = 01, d = 11.

Present state	Input	Output $c_1c_2$	Next state
a (00)	0	00	a (00)
a (00)	1	11	b (10)
b (10)	0	10	c (01)
b (10)	1	01	d (11)
c (01)	0	11	a (00)
c (01)	1	00	b (10)
d (11)	0	01	c (01)
d (11)	1	10	d (11)

Code tree (three-bit input)

Upper branch = input 0, lower branch = input 1; labels are outputs.

                              00 a  (000)
                    00 a ---<
                   /          11 b  (001)
          00 a ---<
         /         \          10 c  (010)
        /           11 b ---<
       /                      01 d  (011)
 start<
       \                      11 a  (100)
        \           10 c ---<
         \         /          00 b  (101)
          11 b ---<
                   \          01 c  (110)
                    01 d ---<
                              10 d  (111)
   bit:    1          2          3

Read along a path: input 101 gives 11, 10, 00, i.e. root (down 11) to b, (up 10) to c, (down 00) to b.

Trellis diagram, input 101 (plus 00 to flush)

      t0     t1     t2     t3     t4     t5
a 00  *      o      o      o      o      *
        \                               /
           \                           /
b 10  o      *      o      *      o   /  o
               \         /   \      /
                  \   /         \  /
c 01  o      o      *      o      *      o


d 11  o      o      o      o      o      o
in:      1      0      1      0      0
out:    11     10     00     10     11

Encoded output for 101: 11 10 00 10 11. Every state in the full trellis has two outgoing branches; after the first two stages the trellis structure repeats.

✓ Answer checked by Claude Opus 5.5 (high effort)

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All Communication Systems chapter 8 questions →

Error detection vs correction; rate ½ convolutional encoder

Error detection vs error correction

Rate-1/2 convolutional encoder (design)

Code tree (three-bit input)

Trellis diagram, input 101 (plus 00 to flush)

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