8051 internal structure and family chart

Internal structure of the 8051

 +------------------------------------------------------+
 |  Interrupt control   +----------+   On-chip           |
 |  (INT0,INT1,T0,T1,   | 4K ROM   |   oscillator        |
 |   serial)            | (code)   |   and clock         |
 |                      +----------+                     |
 |  +--------+  +-----+ +----------+  +----------------+ |
 |  | CPU:   |  | PC  | | 128 B RAM|  | Timer 0, 1     | |
 |  | ALU,   |  |DPTR | | + SFRs   |  | Serial port    | |
 |  | A, B,  |  | SP  | +----------+  | (UART)         | |
 |  | PSW    |  +-----+               +----------------+ |
 |  +--------+       internal bus                         |
 |  +------+ +------+ +------+ +------+  +-------------+  |
 |  | P0   | | P1   | | P2   | | P3   |  | Bus control |  |
 |  +--+---+ +--+---+ +--+---+ +--+---+  +-------------+  |
 +-----|--------|--------|--------|----------------------+
       v        v        v        v
   Port pins P0.0-P0.7 ... P3.0-P3.7 (32 I/O lines)

• CPU: 8-bit ALU, accumulator A, register B, PSW (flags), registers R0-R7 (4 banks), PC, DPTR, stack pointer.
• Memory: 4 KB on-chip ROM and 128 B RAM, plus SFRs.
• Timers/counters: two 16-bit (T0, T1). Serial port: one full-duplex UART.
• Interrupt logic: five sources with two priority levels.
• I/O ports: P0-P3, 32 lines; P0 and P2 also carry the address/data bus for external memory.
• Oscillator and bus control: XTAL1/XTAL2, ALE, PSEN, EA, RST.

8051 family comparison

The 52 series adds Timer 2 and 128 more bytes of RAM; flash versions can be reprogrammed electrically.