8051 minimum circuit and 75% duty pulse

Minimum configuration circuit

The 8051 needs power, a clock and a reset to run; with internal ROM in use (EA = VCC) no other chip is needed.

 Power:  +5V -> pin 40 (VCC), pin 31 (EA); GND -> pin 20

 Reset:  +5V --| |--+-- pin 9 (RST)
                10uF |
                   [8.2k]
                     |
                    GND

 Clock:  pin 19 --+-- 12 MHz crystal --+-- pin 18
                          |                    |
                        33pF                 33pF
                          |                    |
                         GND                  GND

 LED:    pin 8 (P1.7) --[330R]--|>|-- GND
 Switch: pin 2 (P1.1) ---/ --- GND  (open=1, closed=0)

• Power: +5 V at pin 40, GND at pin 20; EA (pin 31) is tied to +5 V to use the internal program memory.
• Clock: a 12 MHz crystal between pins 18 and 19, with two 33 pF capacitors to ground.
• Reset: a 10 uF capacitor from +5 V to RST (pin 9) and an 8.2 k resistor from RST to ground give a power-on reset (a push button is optional).
• LED: P1.7 drives an LED through a 330 ohm resistor to ground (LED on when P1.7 = 1). Port pins can source only a small current through their internal pull-ups, so in practice the LED is often wired from +5 V through the resistor to P1.7 (lit when P1.7 = 0) or driven through a transistor.
• Switch: between P1.1 and ground. Port 1 has internal pull-ups, so P1.1 = 1 when the switch is open and 0 when it is ON (closed).

75 % duty pulse program

The period is 4 ms (250 Hz): P1.7 is high for 3 ms and low for 1 ms, repeated while the switch is ON (P1.1 = 0).

        ORG 0000H
        SETB P1.1          ; make P1.1 an input (switch)
LOOP:   JB P1.1,OFF        ; P1.1 = 1 -> switch open (OFF), no pulse
        SETB P1.7          ; LED pin high  ... start of 3 ms HIGH time
        ACALL D1MS
        ACALL D1MS
        ACALL D1MS
        CLR P1.7           ; LED pin low   ... 1 ms LOW time
        ACALL D1MS
        SJMP LOOP          ; period 4 ms (250 Hz), duty 3/4 = 75 %
OFF:    CLR P1.7           ; keep LED off while the switch is open
        SJMP LOOP

; 1 ms delay at 12 MHz: 2 (ACALL) + 1 + 5 x (1 + 98 x 2 + 2) + 2 (RET) = 1000 cycles
D1MS:   MOV R7,#5
D1:     MOV R6,#98
D2:     DJNZ R6,D2
        DJNZ R7,D1
        RET
        END

D1MS takes exactly 1000 machine cycles at 12 MHz (2 + 1 + 5 x 199 + 2). In a simulator, P1.7 was high for 3.001 ms and low for 1.005 ms (duty 74.9 %). If the switch is open (P1.1 = 1), the LED pin stays low.