Enhanced DRAM core

A conventional DRAM core (an array of capacitor cells with row and column decoders and sense amplifiers) is slow because each access has to read a whole row and then precharge. Enhanced DRAM improves speed without changing the DRAM cell array. It adds circuits around the core that exploit the fact that a whole row is read into the sense amplifiers at once.

Enhancements around the DRAM core

• Fast Page Mode (FPM) DRAM: after a row is opened, several column addresses in the same row are accessed without re-sending the row address, which speeds up sequential access.
• EDO (Extended Data Out) DRAM: the output data is latched and stays valid while the next column address is applied, so successive reads overlap and are faster.
• Synchronous DRAM (SDRAM): a clock synchronises the memory with the system bus, allowing pipelined, burst transfers.
• DDR SDRAM: transfers data on both clock edges, doubling the data rate.
• Rambus DRAM (RDRAM): uses a narrow, high-speed, packet-based bus.
• Cache (Enhanced) DRAM, EDRAM: a small SRAM cache on the chip holds the last accessed row; hits are served at SRAM speed, and the DRAM core is accessed only on misses.

 Address -> [Row/col decoders] -> [DRAM array core]
                                       |
                              [Sense amps + row SRAM buffer]
                                       |
                                    Data out (burst)

All of these give faster access to consecutive data by using the row buffer around the core, at a modest extra cost.