ISA bus protocols

The ISA (Industry Standard Architecture) bus is the 8/16-bit expansion bus of the IBM PC/AT, used with 80x86 processors and clocked at about 8 MHz. It is a synchronous bus with separate address, data and control lines. It uses a compromise strobe/handshake protocol: a transfer normally finishes in a fixed number of clock cycles (like a strobe), but a slow device can stretch it by pulling the ready line low (like a handshake). The processor (or a DMA controller) is the bus master and a card responds as slave.

Main signals:

• Address lines: SA0-SA19 (and LA17-LA23 for 16 MB), data lines SD0-SD15.
• Control: MEMR, MEMW (memory read/write), IOR, IOW (I/O read/write), ALE/BALE (address latch enable).
• I/O CH RDY (CHRDY) (ready line to insert wait states), IRQ lines (interrupts), DRQ/DACK (DMA request and acknowledge), RESET, CLK.

Read cycle (memory or I/O):

1. Cycle C1: the master puts the address on the address lines and asserts ALE/BALE to latch it.
2. Cycle C2: the master asserts MEMR (or IOR) to tell the addressed device to put data on the data bus.
3. Cycle C3: the device places the data on the bus. If the device is slow, it pulls CHRDY low to insert wait states until the data is ready.
4. Cycle C4: the master reads the data and deactivates MEMR/IOR; the cycle ends. A default cycle therefore takes 4 clock cycles, plus any wait states.

Write cycle: the same, but the master puts data on the data lines and asserts MEMW or IOW; the device latches the data, again using CHRDY to add wait states if needed.

DMA: a device raises DRQ; the DMA controller replies with DACK, becomes the master and generates the memory and I/O read/write signals.

Interrupt: a card asserts an IRQ line to the interrupt controller.