Optimization of single-purpose processors

Optimization is the process of improving the design metrics (performance, size, power, cost) of a system by making design trade-offs, since the metrics compete. For a custom single-purpose processor (SPP), optimisation is done at four levels, each with its own opportunities and parameters.

1. Optimising the original program (algorithm)

• Choose a faster algorithm (e.g. GCD by Euclid's subtraction/modulo method instead of trial division).
• Reduce operations: replace multiplication by shifts, remove redundant computation, and pick smaller data types (bit widths).

2. Optimising the FSMD

• Scheduling: merge states so that independent operations run in the same state (more parallelism, fewer clock cycles).
• Removing unnecessary states: e.g. a wait state or a separate state for a trivial assignment.
• Parameters: number of states, clock cycles per task, clock period.

3. Optimising the datapath

• Share functional units (one ALU used in different states) to reduce size, at the cost of extra muxes and more states.
• Use multi-functional units, remove unused registers, and reduce bit widths.
• Parameters: number of registers/ALUs, multiplexer count, critical path (clock period).

4. Optimising the FSM (controller)

• State encoding: binary (fewest flip-flops, more logic) versus one-hot (more flip-flops, faster logic).
• State minimisation: merge equivalent states.
• Parameters: flip-flops, gates, delay.

Example: summing the elements of an array in a loop

Original FSMD:        Optimised FSMD:
 S1: i = 0             S1: i = 0, s = 0
 S2: s = 0             S2: if i<n: s = s+a[i]; i = i+1
 S3: if i<n ..         (5 states -> 2 states, fewer cycles)
 S4: s = s+a[i]
 S5: i = i+1

Merging S1/S2 and S3/S4/S5 reduces the cycle count (performance up) but needs two independent adders working in the same state (size up). Sharing a single adder instead would reduce size but cost extra cycles. The designer therefore picks the point that best satisfies the constraints.