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Super scalar versus VLIW architecture

Explain the concept of pipelining. Differentiate super scalar and VLIW architecture.

Pipelining

Pipelining divides instruction execution into stages (fetch, decode, execute, memory access, write-back). A new instruction enters the first stage each clock while earlier ones occupy later stages, so several instructions are in progress together and throughput approaches one instruction per cycle.

 Inst 1: IF ID EX MEM WB
 Inst 2:    IF ID EX MEM WB
 Inst 3:       IF ID EX MEM WB

Superscalar versus VLIW

Both issue several instructions per clock using multiple functional units (parallel pipelines); they differ in who finds the parallelism.

PointSuperscalarVLIW (Very Long Instruction Word)
Parallelism found byHardware at run time (dynamic scheduling)Compiler at compile time (static scheduling)
Instruction formatOrdinary, variable instructionsOne very long word (e.g. 128 bits) containing several operations
Hardware complexityHigh (dependency checking, reorder, branch prediction)Low (no scheduling logic)
Power and areaHigherLower
Compiler complexitySimplerComplex; must schedule well
Code sizeSmallerLarger (NOPs for unused slots)
Binary compatibilityGood across generationsPoor; recompilation needed
ExamplesPentium, ARM Cortex-A, PowerPCTI TMS320C6x DSP, Itanium

Result: superscalar suits general computing; VLIW suits embedded and DSP, where the program is known beforehand and power matters.

✓ Answer checked by Claude Opus 5.5 (high effort)

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