- 2071 Bhadra · 4+4+2 marks
- Year not given
Compaction vs coalescing; paging; TLB
Short answer
Compaction relocates processes to create one large free block; coalescing merges adjacent free blocks without moving processes. Paging maps logical address by splitting into page number and offset; page table gives frame number, then physical address = frame×size + offset. For 4KB pages, address 9000 → page 2, offset 808 → physical 4904. TLB caches recent translations to speed access.
Differentiate compaction and coalescing techniques. How is logical address mapped to real physical address by paging technique? Explain with suitable example. What is the role of TLB?
Compaction vs coalescing
| Point | Coalescing | Compaction |
|---|---|---|
| Meaning | Merging adjacent free blocks into one larger free block | Moving all allocated blocks together so all free space forms one block |
| When | When a block is freed next to another free block | When free space is scattered and no hole is large enough |
| Moves processes? | No | Yes, processes are relocated |
| Cost | Cheap | Expensive (copying memory, updating base registers) |
| Needs dynamic relocation? | No | Yes |
| Effect | Reduces fragmentation partly | Removes external fragmentation fully |
Example: holes of 20 K and 30 K that are adjacent become one 50 K hole by coalescing. Holes of 10 K, 20 K, 15 K separated by processes become one 45 K hole by compaction.
Paging and address mapping
Physical memory is divided into fixed frames and logical memory into pages of the same size. A logical address has a page number p and offset d. The page table maps p to a frame number f; physical address = f × page size + d.
CPU: [ p | d ] --> page table[p] = f --> [ f | d ] --> memory
Example: page size 1 KB (1024), logical address 2500, page table: 0→5, 1→2, 2→7.
- p = 2500 / 1024 = 2, d = 2500 mod 1024 = 452.
- Page 2 is in frame 7.
- Physical address = 7 × 1024 + 452 = 7620.
Role of TLB
The TLB (Translation Lookaside Buffer) is a small, fast associative cache inside the MMU holding recent (page, frame) pairs. Without it, each memory access needs two accesses (page table, then data). The MMU first searches the TLB for p: on a hit the frame is obtained at once; on a miss the page table in memory is read and the entry is loaded into the TLB. With hit ratio 90%, TLB time 20 ns and memory 100 ns, effective access time = 0.9×120 + 0.1×220 = 130 ns instead of 200 ns.
✓ Answer checked by Claude Opus 5.5 (high effort)
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