GaAs FET amplifier for maximum gain at 4 GHz

For maximum gain the transistor must be conjugate matched at both ports at once (bilateral design): Γs = ΓMS and ΓL = ΓML, with lossless matching networks to the 50 Ω source and load.

Δ   = S11·S22 − S12·S21
K   = (1 − |S11|² − |S22|² + |Δ|²) / (2|S12·S21|)
Unconditionally stable if K > 1 and |Δ| < 1
GTU,max = 1/(1−|S11|²) · |S21|² · 1/(1−|S22|²)
GT,max  = (|S21|/|S12|)·(K − √(K² − 1))
B1 = 1 + |S11|² − |S22|² − |Δ|²,  C1 = S11 − Δ·S22*
B2 = 1 + |S22|² − |S11|² − |Δ|²,  C2 = S22 − Δ·S11*
ΓMS = [B1 − √(B1² − 4|C1|²)] / (2C1)
ΓML = [B2 − √(B2² − 4|C2|²)] / (2C2)

Step 1: Stability

S11·S22 = 0.72×0.73∠(−116°−54°) = 0.5256∠−170°
        = −0.5176 − j0.0913
S12·S21 = 0.03×2.60∠(57°+76°) = 0.0780∠133°
        = −0.0532 + j0.0570
Δ = −0.4644 − j0.1483 = 0.4875∠−162.29°
K = (1 − 0.5184 − 0.5329 + 0.2377)/(2×0.0780)
  = 0.1864/0.1560 = 1.195

K = 1.195 > 1 and |Δ| = 0.488 < 1 → unconditionally stable (μ = 1.040). Stability circles (CS = 1.320∠123.41°, RS = 0.278; CL = 1.304∠61.03°, RL = 0.264) lie completely outside the Smith chart.

Step 2: Source and load reflection coefficients

B1 = 1 + |S11|² − |S22|² − |Δ|² = 0.7478
C1 = S11 − ΔS22* = 0.3704∠−123.41°
ΓMS = [B1 − √(B1² − 4|C1|²)]/(2C1) = 0.872∠123.41°
B2 = 1 + |S22|² − |S11|² − |Δ|² = 0.7768
C2 = S22 − ΔS11* = 0.3850∠−61.03°
ΓML = [B2 − √(B2² − 4|C2|²)]/(2C2) = 0.876∠61.03°

Corresponding impedances: Zs = 4.41 + j26.76 Ω, ZL = 12.63 + j83.43 Ω. Check: Γin with ΓML = 0.872∠−123.41° = ΓMS*, so the input is conjugate matched.

Step 3: Gains

GS = 1/(1 − |ΓMS|²)             = 4.166 → 6.20 dB
G0 = |S21|² = 2.60²             = 6.76  → 8.30 dB
GL = (1 − |ΓML|²)/|1 − S22ΓML|² = 1.665 → 2.21 dB
GT,max = 6.20 + 8.30 + 2.21 = 16.71 dB
Check: (2.60/0.03)(1.195 − √(1.195²−1)) = 46.88
     → 16.71 dB  ✓

Step 4: Matching networks (shunt open stub + series 50 Ω line)

Each network: from the 50 Ω termination, a shunt open-circuited stub moves the point to the circle |Γ| = 0.872 (or 0.876), then a series 50 Ω line rotates it to the required angle.

For y = 1 + jb to lie on |Γ| = m: b = √(4m²/(1 − m²)).

Input network (Γs = 0.872∠123.4°):

b = +3.559 → stub: tan βl = 3.559 → l = 0.206λ (open)
Γ after stub = 0.872∠−150.67°
Series line rotates (toward generator = transistor):
2βd = −150.67° − 123.41° + 360° = 85.92°
d = 85.92°/720° = 0.119λ

Output network (ΓL = 0.876∠61.0°):

b = +3.638 → stub: l = 0.207λ (open)
Γ after stub = 0.876∠−151.20°
2βd = −151.20° − 61.03° + 360° = 147.77°
d = 147.77°/720° = 0.205λ

50Ω src  0.119λ line     0.205λ line  50Ω load
 o---+---=========--[FET]--=========---+---o
     |                                 |
  open stub                        open stub
   0.206λ                           0.207λ

Step 5: Bias and realisation

• DC bias (e.g. VDS ≈ 3–5 V for a GaAs FET) through λ/4 high-impedance lines or RF chokes; DC blocking capacitors at the ports.
• On a microstrip substrate, λ is replaced by the guided wavelength λg at 4 GHz to get physical lengths.
• Simulate over the band: the gain is maximum (16.7 dB) at 4.0 GHz and falls away from it because the stubs are frequency dependent.

Unilateral comparison

GTU,max = 2.076 × 6.76 × 2.141 = 30.05 (14.78 dB). U = 0.182, so the unilateral model is inaccurate; the bilateral design above is required for true maximum gain.

Answer: K = 1.195 (stable), ΓMS = 0.872∠123°, ΓML = 0.876∠61°, GT,max = 46.9 ≈ 16.7 dB; input: stub 0.206λ + line 0.119λ; output: stub 0.207λ + line 0.205λ.