Pulse stuffing in TDM synchronization

Pulse stuffing (bit stuffing or justification) is the addition of extra non-information bits to a digital tributary so that its rate exactly matches the slot rate offered by a higher-order TDM multiplexer. It is the way plesiochronous digital hierarchy (PDH) multiplexers handle inputs whose clocks are nominally equal but not exactly the same.

Why it is needed

When several tributaries (e.g. four E1 streams into an E2) come from different places, each has its own clock with a small tolerance (±50 ppm for E1). The multiplexer reads all tributaries at one common rate. If a tributary is a little slower than the read rate the multiplexer buffer runs empty (underflow); if it is faster it overflows. Either case causes slips – lost or repeated bits – and loss of frame alignment.

Role in maintaining synchronisation (positive stuffing)

1. The multiplexer runs each tributary slot at a rate slightly higher than the maximum possible tributary rate. That is why the higher-order rate is more than the sum of the inputs (8.448 > 4 × 2.048 Mbps).
2. Each input is written into an elastic buffer with its own clock and read out with the multiplexer clock.
3. A phase comparator watches the buffer fill. When it is nearly empty, the multiplexer inserts a stuff (dummy) bit in a reserved position instead of a data bit.
4. Stuffing control (justification control) bits in the frame tell the receiver whether the reserved position holds a stuff bit or data. They are sent several times (e.g. 3 times) and decoded by majority vote, so a single bit error does not cause a wrong decision.
5. In effect each tributary gets a variable number of data bits per frame, matching its actual rate, while the aggregate stream has a fixed rate.

 tributary in (slightly slow)
 bits:  d d d d d d d d d d d ...
 MUX frame (fixed rate):
 | C | d d d d | C | d d d d | C | S/d d d d |
   C = stuffing control bits (repeated, e.g. 3)
   S/d = stuff bit if C=111, data bit if C=000

How it ensures accurate data transmission

• At the receiver (demultiplexer): frame alignment locates the control bits; majority logic decides whether a stuff bit is present; stuff bits are removed, and the remaining data bits are written into a buffer.
• A phase-locked loop smooths the gapped clock and regenerates the original tributary clock, so the tributary leaves the demultiplexer at exactly its original rate with no bits lost or added.
• Thus no slips occur even though the tributary clocks differ; only a small waiting-time jitter remains, which the PLL keeps within limits.
• Repetition of control bits protects against wrong de-stuffing, which would otherwise shift all following bits and corrupt the channel.

Other types: negative stuffing (sending an extra data bit in a spare position when the tributary is fast) and positive/zero/negative justification, as used in SDH pointers.