SPC and dual processor architecture

Stored program control

Stored Program Control (SPC) is the control of an exchange by a processor running programs stored in memory. Call processing, routing, charging and maintenance are done in software, so new features can be added by changing the program.

Dual-processor architecture in centralised SPC

In centralised SPC one processor controls the whole exchange, so a failure would stop all calls. The processor is therefore duplicated. The two processors (P1 and P2) share or copy the memory and work in one of three modes.

  +------+   +------+
  |  P1  |   |  P2  |
  +--+---+   +---+--+
     |  +----+   |
     +--|Comp|---+     (comparator in
     |  +----+   |      sync duplex)
  +--+---+   +---+--+
  |  M1  |   |  M2  |   (memories)
  +------+   +------+
        \     /
     exchange hardware

1. Standby mode

• One processor is active; the other is idle on standby.
• The standby takes over when the active one fails.
• The memory is shared or the active processor regularly copies its data to a secondary store, so the standby can reload the current call data.
• Simple, but calls being set up at the time of failure may be lost.

2. Synchronous duplex mode

• Both processors run the same program at the same time, each with its own memory, and get the same inputs.
• A comparator checks their outputs after each step. If they agree, normal working continues.
• On a mismatch, both run diagnostic programs; the faulty one is taken out of service and the healthy one continues alone.
• Gives fast fault detection and no loss of calls, but transient faults may cause needless check routines.

3. Load-sharing mode

• Each processor handles part of the traffic (e.g. calls are given to them alternately or at random).
• They share a common memory and use an exclusion device (ED) so both do not seize the same resource at once.
• If one fails, the other carries the full load (with possible reduced grade of service at the busy hour).
• Gives higher call-handling capacity than standby or synchronous modes.

Availability

For one processor, $A = \dfrac{MTBF}{MTBF + MTTR}$. For a dual system the mean time between system failures becomes

$$MTBF_D = \frac{MTBF^2}{2\,MTTR}$$

so unavailability falls from about $MTTR/MTBF$ to about $2\,MTTR^2/MTBF^2$. This large gain is why all centralised SPC exchanges use duplicated processors.