Digital Switching

A digital telephone exchange is a stored-program-controlled (SPC) exchange in which speech is switched in digital (PCM) form, using time and space switching of 64 kbps channels, under the control of computer processors. Examples: Alcatel E10, Siemens EWSD, Ericsson AXE, and the exchanges installed by Nepal Telecom.

Block diagram

 analogue      +-------------+  +------+
 subscribers --| Subscriber  |--|      |
 (2-wire)      | line units  |  | conc-|   +-----------+
 (BORSCHT)     |  + codec    |  |entr. |===|           |
               +-------------+  +------+   |  Digital  |
 digital trunks (E1)--[trunk interface]====| switching |
 analogue trunks--[ATI + codec]===========| network   |
                                           |  (TST)    |
 tones/announcements --[tone generator]====|           |
 signalling --[CAS/CCS (SS7) units]=======|           |
                                           +-----+-----+
                                                 |
                 +-------------------------------+---+
                 |  Control subsystem (processors,   |
                 |  memory, stored programs)         |
                 +----+-------------------------+----+
                      |                         |
              [O&M terminal, billing]   [network sync clock]

Main blocks

1. Subscriber line interface (line card). Each analogue line needs the BORSCHT functions:
   • Battery feed (−48 V DC for the telephone),
   • Overvoltage protection (lightning, power-line contact),
   • Ringing (75 V, 25 Hz AC applied to the line),
   • Supervision (detecting off-hook, on-hook, dial pulses),
   • Coding (codec: A-law PCM at 64 kbps, with filters),
   • Hybrid (2-wire to 4-wire conversion),
   • Testing (access for line tests).
2. Concentrator / remote line unit. Since only a fraction of subscribers are busy at once, many lines (e.g. 128–1000) are concentrated onto fewer PCM channels (E1 links) to the switching network. Remote units can be placed near subscriber clusters.
3. Trunk interfaces. Digital trunks (E1, 2.048 Mbps, HDB3) are connected directly after frame alignment and clock adaptation; analogue trunks need codecs and signalling conversion.
4. Digital switching network. Usually a TST (time–space–time) or multi-stage network. Time switches (time slot interchangers) move a sample from one time slot to another using speech and control memories; space switches connect a time slot on one PCM highway to the same slot on another. This connects any 64 kbps channel to any other. The network is duplicated for reliability.
5. Signalling equipment. Receivers for dial pulses and DTMF, CAS units (E1 TS16) and common channel signalling (SS7) terminals for inter-exchange signalling.
6. Service circuits. Tone generators (dial, busy, ring-back), announcement machines, conference bridges.
7. Control subsystem. Duplicated processors with stored programs carry out call processing, routing translation, charging and resource management. Control may be centralised or distributed.
8. Operation and maintenance (O&M) and billing. Terminals for subscriber data changes, traffic measurement, fault alarms, diagnostics and call detail records.
9. Synchronisation. A clock locked to the national network clock keeps all PCM links in step to avoid slips.

Working principle (a local call)

1. Off-hook detection: subscriber A lifts the handset; loop current flows; the line card's supervision scans and reports to the processor.
2. Dial tone: the processor checks A's class of service, assigns a free path and a digit receiver, and connects dial tone.
3. Digit reception: dialled digits (pulses or DTMF) are received and stored; dial tone is removed after the first digit.
4. Analysis and routing: the processor translates the number. For a local number it checks B's line; for a distant number it selects an outgoing trunk and sends signalling (e.g. SS7 IAM).
5. Path set-up: a free time slot path through the TST network is found and the speech and control memories are written.
6. Ringing: ringing current is sent to B and ring-back tone to A.
7. Answer: when B lifts the handset, ringing is tripped, the speech path is through-connected and charging starts.
8. Conversation: speech from each phone is coded to 64 kbps, switched digitally in its time slots and decoded at the other line card.
9. Clear-down: on on-hook, the processor releases the path, stops charging and records the call details.

Advantages

• No noise build-up; uniform digital quality and easy integration with digital transmission (no codec at each trunk).
• Small size, low power, fast set-up, high reliability (duplicated control).
• Many subscriber services (call waiting, forwarding, conference, abbreviated dialling), easy changes by software, centralised O&M and accurate billing.
• Supports ISDN, data and common channel signalling.

In centralised SPC, a single processor controls the whole exchange, so its failure would stop all calls. To give high availability (an exchange may be down only about 2 hours in 40 years), the central processor is duplicated. The two processors work in one of three modes.

1. Standby mode

 +-------+         +-------+
 | P1    |         | P2    |
 |active |         |standby|
 +---+---+         +---+---+
     +----[shared memory / disk]----+
           |
     exchange equipment

• One processor (P1) is active and handles all calls; the other (P2) is idle in standby.
• Both have access to a common secondary memory; the active one periodically copies the exchange state (call data, tables) to it.
• When P1 fails, P2 takes over, loads the latest state and continues.
• Cold standby: P2 starts from the last saved data, so calls being set up are lost. Hot standby: P2 is kept updated and takes over almost at once.
• Simple, but takeover takes time and transient calls may be lost.

2. Synchronous duplex (match) mode

 +-------+   comparator   +-------+
 | P1    |<------C------->| P2    |
 |  M1   |                |  M2   |
 +---+---+                +---+---+
     +-------- exchange --------+

• Both processors run the same program on the same data, in step, each with its own memory (M1, M2).
• A comparator checks their results continuously. One processor's outputs actually control the exchange.
• If the results disagree, a fault is suspected; both run diagnostics. The faulty processor is isolated and the good one continues alone, with almost no loss of calls.
• Gives fast fault detection and no takeover delay, but both processors do the same work, so no extra capacity, and a transient fault may be hard to locate.

3. Load-sharing mode

 +-------+   exclusion    +-------+
 | P1    |<-----ED------->| P2    |
 | calls |   (shared      | calls |
 | 1,3,5 |    data)       | 2,4,6 |
 +---+---+                +---+---+
     +-------- exchange --------+

• Each processor handles part of the traffic; an incoming call is given randomly or in turn to one of them.
• Both share the exchange resources and data; an exclusion device (ED) stops them from seizing the same resource at the same time.
• Each can handle the full load. If one fails, the other carries all the traffic (with possible congestion at peak).
• Gives higher capacity in normal operation and good reliability, but software is more complex.

Comparison

Advantages of multi-stage over single-stage switching

• Far fewer crosspoints: a single-stage $N \times N$ switch needs $N^2$ crosspoints (e.g. $10^6$ for 1000 lines); a three-stage switch needs only a small fraction, so cost and size fall.
• Better crosspoint utilisation: in a single stage only $N/2$ of $N^2$ crosspoints can be busy at once; in multi-stage each crosspoint is shared by many connections.
• Alternative paths: a call can go through any of several middle-stage arrays, so failure of one crosspoint does not isolate a subscriber (better reliability).
• Modular growth: capacity can be expanded by adding arrays.
• Concentration and expansion can be built into the stages to suit traffic.
• Cost: some blocking may occur, and path search (control) is more complex.

TST switching

A Time–Space–Time (TST) switch is a three-stage digital switching network: an incoming time stage, a space stage in the middle, and an outgoing time stage. It is the most common structure in large digital exchanges.

 incoming     T stage      S stage       T stage   outgoing
 highways   (time slot   (crosspoint   (time slot  highways
            interchange)   matrix)    interchange)
 PCM 1 --->[ TSI ]--->+-------------+--->[ TSI ]---> PCM 1
 PCM 2 --->[ TSI ]--->|  N x N      |--->[ TSI ]---> PCM 2
  ...                 |  space sw.  |
 PCM N --->[ TSI ]--->+-------------+--->[ TSI ]---> PCM N
 slot i  -> slot j (internal) -> slot j -> slot m

Operation (connect slot $i$ of PCM 1 to slot $m$ of PCM N):

1. First time stage: the time slot interchanger (TSI) on PCM 1 writes incoming samples into its speech memory in order and reads the sample of slot $i$ out in a free internal slot $j$ (chosen by the control).
2. Space stage: in internal slot $j$ the crosspoint connecting row 1 to column N is closed (set by the space-switch control memory), passing the sample to the outgoing side. The same crosspoint is reused by other connections in other slots.
3. Second time stage: the TSI on output highway N stores the sample and reads it out in the required outgoing slot $m$.
4. The reverse direction uses a related internal slot (often $j + c/2$) so both directions are set together.

Because the space stage only needs to find one free internal slot common to both links, the many internal time slots act like many middle-stage arrays, giving very low blocking at low cost. The time stages can also expand ($l > c$ internal slots) to reduce blocking further.

Blocking probability of TST (Lee graph)

           slot 1
       +--- ... ---+
  A ---+--- slot j-+--- B     l parallel paths
       +--- ... ---+          (internal slots)
           slot l

Let $p$ = occupancy of an incoming channel, $c$ = channels per highway, $l$ = internal slots, time expansion $\alpha = l/c$. Each internal link is busy with probability $p' = p/\alpha$. A path is blocked if either of its two links is busy: $1-(1-p')^2$. The call is blocked only if all $l$ paths are blocked:

$$\begin{aligned} p' &= \frac{p}{\alpha},\quad \alpha = \frac{l}{c} \\ P_B(\text{TST}) &= \left[1 - (1-p')^2\right]^{l} \end{aligned}$$

Example: $p = 0.2$, $l = c = 32$: $P_B = (1 - 0.8^2)^{32} = 0.36^{32} \approx 6.3 \times 10^{-15}$, practically non-blocking.

Clos network

A Clos network is a three-stage (multi-stage) switching network, proposed by Charles Clos (1953), in which $N$ inputs are divided into $N/n$ first-stage arrays of size $n \times k$, connected to $k$ middle arrays of size $\frac{N}{n} \times \frac{N}{n}$, which connect to $N/n$ third-stage arrays of size $k \times n$. Every array of one stage has exactly one link to every array of the next stage.

$$\begin{aligned} N_x &= \underbrace{\tfrac{N}{n}(nk)}_{\text{stage 1}} + \underbrace{k\left(\tfrac{N}{n}\right)^2}_{\text{stage 2}} + \underbrace{\tfrac{N}{n}(kn)}_{\text{stage 3}} \\ &= 2Nk + k\left(\frac{N}{n}\right)^2 \end{aligned}$$

Clos showed that the network is strictly non-blocking when $k = 2n - 1$ (worst case: $n-1$ other inputs of the calling array and $n-1$ outputs of the called array use different middle arrays, so one more is needed). With the best choice $n \approx \sqrt{N/2}$, the minimum is $N_x \approx 4N(\sqrt{2N} - 1)$, much less than $N^2$.

Blocking probability of STS

 STS:     S (N x k) -> T (k TSI modules) -> S (k x N)
 Lee graph: k parallel paths, each = 2 links in series

In STS, a call from input highway A to output highway B in given slots can go through any of the $k$ time-switch modules. Each path uses a link from the first space stage to a module and a link from the module to the second space stage. With link occupancy $p' = p/\beta$ ($\beta = k/N$ space expansion):

• Probability a link is free $= 1 - p'$; both links of a path free $= (1-p')^2$.
• Path blocked $= 1 - (1-p')^2$; all $k$ paths blocked:

$$\begin{aligned} p' &= \frac{p}{\beta},\quad \beta = \frac{k}{N} \\ P_B(\text{STS}) &= \left[1 - (1-p')^2\right]^{k} \end{aligned}$$

Blocking probability of TST

 TST:     T (c -> l slots) -> S (N x N) -> T (l -> c)
 Lee graph: l parallel paths (internal time slots)

In TST, the path from A to B passes through the space stage in any of the $l$ internal time slots. Each path uses one internal slot on A's highway and the same slot on B's highway. With time expansion $\alpha = l/c$, $p' = p/\alpha$, and by the same argument:

$$\begin{aligned} p' &= \frac{p}{\alpha},\quad \alpha = \frac{l}{c} \\ P_B(\text{TST}) &= \left[1 - (1-p')^2\right]^{l} \end{aligned}$$

Comparison

Since the number of paths in TST equals the number of internal time slots $l$ (32 to several hundred), while in STS it equals the number of time-switch modules $k$ (usually small), TST blocking is far lower for the same hardware. Example with $p' = 0.2$:

$$\begin{aligned} \text{STS},\ k = 8 &: \ (1-0.8^2)^{8} = 0.36^{8} \approx 2.8 \times 10^{-4} \\ \text{TST},\ l = 32 &: \ (1-0.8^2)^{32} = 0.36^{32} \approx 6.3 \times 10^{-15} \end{aligned}$$

Advantages of multi-stage switching

• Far fewer crosspoints: a single-stage $N \times N$ switch needs $N^2$ crosspoints (e.g. $10^6$ for 1000 lines); a three-stage switch needs only a small fraction, so cost and size fall.
• Better crosspoint utilisation: in a single stage only $N/2$ of $N^2$ crosspoints can be busy at once; in multi-stage each crosspoint is shared by many connections.
• Alternative paths: a call can go through any of several middle-stage arrays, so failure of one crosspoint does not isolate a subscriber (better reliability).
• Modular growth: capacity can be expanded by adding arrays.
• Concentration and expansion can be built into the stages to suit traffic.
• Cost: some blocking may occur, and path search (control) is more complex.

TST switch

 incoming     T stage      S stage       T stage   outgoing
 highways   (time slot   (crosspoint   (time slot  highways
            interchange)   matrix)    interchange)
 PCM 1 --->[ TSI ]--->+-------------+--->[ TSI ]---> PCM 1
 PCM 2 --->[ TSI ]--->|  N x N      |--->[ TSI ]---> PCM 2
  ...                 |  space sw.  |
 PCM N --->[ TSI ]--->+-------------+--->[ TSI ]---> PCM N
 slot i  -> slot j (internal) -> slot j -> slot m

An incoming time slot $i$ is moved by the first TSI to a free internal slot $j$, passed through the space matrix in slot $j$, and moved by the outgoing TSI to the wanted slot $m$. Blocking happens only if no internal slot is free on both the input and output highways. With $l$ internal slots and $p' = p\,c/l$:

$$\begin{aligned} p' &= \frac{p}{\alpha},\quad \alpha = \frac{l}{c} \\ P_B(\text{TST}) &= \left[1 - (1-p')^2\right]^{l} \end{aligned}$$

STS switch

 incoming    S stage      T stage      S stage   outgoing
 PCM 1 --->+--------+--->[ TSI 1 ]--->+--------+---> PCM 1
 PCM 2 --->| N x k  |--->[ TSI 2 ]--->| k x N  |---> PCM 2
  ...      | space  |     ...         | space  |
 PCM N --->+--------+--->[ TSI k ]--->+--------+---> PCM N

The first space stage connects the incoming highway (in its own slot) to one of $k$ time switches; the TSI moves the sample to the outgoing slot; the second space stage connects it to the outgoing highway. Blocking happens if none of the $k$ modules has both links free. With $p' = p/\beta$:

$$\begin{aligned} p' &= \frac{p}{\beta},\quad \beta = \frac{k}{N} \\ P_B(\text{STS}) &= \left[1 - (1-p')^2\right]^{k} \end{aligned}$$

Comparison of TST and STS

Example ($p' = 0.2$): STS with $k = 8$ gives $P_B = 0.36^8 \approx 2.8 \times 10^{-4}$, while TST with $l = 32$ gives $0.36^{32} \approx 6.3 \times 10^{-15}$. Hence TST is preferred for large exchanges.

Advantages of multi-stage switching over single-stage

• Far fewer crosspoints: a single-stage $N \times N$ switch needs $N^2$ crosspoints (e.g. $10^6$ for 1000 lines); a three-stage switch needs only a small fraction, so cost and size fall.
• Better crosspoint utilisation: in a single stage only $N/2$ of $N^2$ crosspoints can be busy at once; in multi-stage each crosspoint is shared by many connections.
• Alternative paths: a call can go through any of several middle-stage arrays, so failure of one crosspoint does not isolate a subscriber (better reliability).
• Modular growth: capacity can be expanded by adding arrays.
• Concentration and expansion can be built into the stages to suit traffic.
• Cost: some blocking may occur, and path search (control) is more complex.

Crosspoint calculation

Reading of the data (assumed): the first stage has 3 arrays of 4 input lines each, so $N = 3 \times 4 = 12$ lines and $n = 4$, and there are $k = 5$ second-stage (middle) arrays. The network is symmetric (third stage = mirror of first).

Array sizes:

• First stage: $N/n = 3$ arrays of $n \times k = 4 \times 5$.
• Second stage: $k = 5$ arrays of $\frac{N}{n} \times \frac{N}{n} = 3 \times 3$.
• Third stage: 3 arrays of $k \times n = 5 \times 4$.

  stage 1 (3 x [4x5])  stage 2 (5 x [3x3])  stage 3
 4 in->[4x5]-+-----> [3x3] -----+->[5x4]-> 4 out
             |-----> [3x3] -----|
 4 in->[4x5]-+-----> [3x3] -----+->[5x4]-> 4 out
             |-----> [3x3] -----|
 4 in->[4x5]-+-----> [3x3] -----+->[5x4]-> 4 out
 each 4x5 array has 1 link to each of the 5 middle
 arrays; each middle array has 1 link to each 5x4

$$\begin{aligned} N_x &= 2Nk + k\left(\frac{N}{n}\right)^2 \\ \text{Stage 1} &= 3 \times (4 \times 5) = 60 \\ \text{Stage 2} &= 5 \times (3 \times 3) = 45 \\ \text{Stage 3} &= 3 \times (5 \times 4) = 60 \\ N_x &= 60 + 45 + 60 = 165 \end{aligned}$$

Answer: 165 crosspoints (60 + 45 + 60).

Remarks:

• A single-stage $12 \times 12$ matrix needs $12^2 = 144$ crosspoints; for such a small $N$ the three-stage network gives no saving. The saving appears for large $N$, e.g. $N = 128$, $n = 8$, $k = 15$ needs 7680 crosspoints against 16 384.
• With $k = 5 < 2n - 1 = 7$, this network is blocking; a strictly non-blocking Clos version needs $k = 7$, i.e. $2(12)(7) + 7(3)^2 = 231$ crosspoints.

Role of time switches

A time switch (time slot interchanger, TSI) moves PCM samples from one time slot to another on the same highway.

 incoming slots -> [speech memory] -> outgoing slots
   write in order     ^ read address
                [control memory]

• Incoming samples are written into a speech memory in slot order (sequential write) and read out in the order set by a control memory (random read), or the reverse.
• It connects channel $i$ to channel $j$ on the same highway with a delay of up to one frame (125 µs).
• Built from RAM, so it is cheap, and it is non-blocking for one highway; the size is limited by memory speed ($c$ slots × 2 accesses within 125 µs).

Role of space switches

A space switch is a crosspoint matrix (electronic gates) that connects an input highway to an output highway, keeping the same time slot.

• Each crosspoint is opened or closed every time slot according to its control memory, so it is shared by many calls (time-shared space switching).
• It enlarges the switch to many highways but cannot change time slots; used alone it blocks when two calls need the same output in the same slot.

How combinations enhance capability

Real exchanges have hundreds of highways, so time and space switches are combined in multi-stage networks:

• TS / ST (two stage): simple, but blocking is high.
• TST (time–space–time): incoming TSI moves the call to any free internal slot, the space stage crosses highways, the outgoing TSI moves it to the wanted slot. The number of alternative paths equals the number of internal slots, so blocking is very low and memory is cheap. Standard in large exchanges.
• STS (space–time–space): space stages spread calls over $k$ time modules; suits smaller systems.
• TSST / TSSST: two or more space stages in the middle allow very large numbers of highways (large transit exchanges) without huge single matrices.
• STTS: two time stages in the middle give more slot-changing freedom and paths between groups of highways, useful in modular/distributed designs.

Benefits of these combinations:

1. Scalability: tens of thousands of lines and trunks switched in one network by adding modules.
2. Low blocking: many alternative paths (internal slots × middle arrays); with time expansion near non-blocking.
3. Lower cost and size: fewer crosspoints; most switching done in cheap RAM.
4. Reliability: alternative paths and duplicated planes let traffic avoid faults.
5. Flexibility: supports any-to-any connection of 64 kbps channels, broadcast/conference connections and $n \times 64$ kbps data paths, which digital networks and ISDN need.

Crosspoint and switching array

A crosspoint is the basic switching element at the intersection of an input line and an output line; when it is closed (a relay contact, reed or electronic gate) it connects that input to that output. A switching array (matrix) is a rectangular arrangement of crosspoints with $N$ inputs and $M$ outputs ($N \times M$ crosspoints); any input can be connected to any free output. A single-stage $N \times N$ array needs $N^2$ crosspoints (or $N(N-1)/2$ if folded), which grows too quickly for large exchanges.

        out1 out2 out3
 in1 ----x----x----x---
 in2 ----x----x----x---    x = crosspoint
 in3 ----x----x----x---

Three-stage switching

The $N$ inputs are divided into groups of $n$.

  first stage      middle stage     third stage
 (N/n arrays,     (k arrays,       (N/n arrays,
   n x k)        N/n x N/n)          k x n)
 n -->[n x k]--+->[N/n x N/n]--+-->[k x n]--> n
 n -->[n x k]--+->[N/n x N/n]--+-->[k x n]--> n
   ...         +->   ...       +-->   ...
 n -->[n x k]--+->[N/n x N/n]--+-->[k x n]--> n
  (every first-stage array has one link to
   every middle array, and so on)

• Stage 1: $N/n$ arrays, each $n \times k$.
• Stage 2: $k$ arrays, each $\frac{N}{n} \times \frac{N}{n}$.
• Stage 3: $N/n$ arrays, each $k \times n$.

Each input reaches any output through any one of the $k$ middle arrays, so there are $k$ alternative paths. Total crosspoints:

$$\begin{aligned} N_x &= \underbrace{\tfrac{N}{n}(nk)}_{\text{stage 1}} + \underbrace{k\left(\tfrac{N}{n}\right)^2}_{\text{stage 2}} + \underbrace{\tfrac{N}{n}(kn)}_{\text{stage 3}} \\ &= 2Nk + k\left(\frac{N}{n}\right)^2 \end{aligned}$$

If $k = 2n - 1$ the network is strictly non-blocking (Clos); if $k < 2n-1$ some blocking occurs but the cost is lower.

Example calculation

Take $N = 128$ lines, $n = 8$ (so $N/n = 16$), non-blocking $k = 2n - 1 = 15$:

$$\begin{aligned} \text{Stage 1} &= 16 \times (8 \times 15) = 1920 \\ \text{Stage 2} &= 15 \times (16 \times 16) = 3840 \\ \text{Stage 3} &= 16 \times (15 \times 8) = 1920 \\ N_x &= 2(128)(15) + 15(16)^2 = 7680 \end{aligned}$$

A single-stage $128 \times 128$ switch would need $128^2 = 16\,384$ crosspoints. The three-stage switch saves about 53 % while still being non-blocking. Here $n = 8 = \sqrt{N/2}$ is the optimum, and the result equals $4N(\sqrt{2N} - 1) = 4(128)(15) = 7680$.

Answer: 7680 crosspoints for a 128-line non-blocking three-stage switch (vs 16 384 single-stage).

PCM (digital) switching

In PCM switching, speech is switched in its digital form: 64 kbps PCM samples are moved between time slots and highways by time and space switches, without converting back to analogue.

Advantages

• Direct integration with digital PCM transmission (E1/T1): no codec or 2W/4W conversion at every exchange, so no noise or loss build-up.
• Time switches made of cheap RAM; very few crosspoints; small size and low power.
• Four-wire switching throughout, so no hybrid echo problems inside the network.
• Easy to switch data and $n \times 64$ kbps channels; supports ISDN.
• Fast connection, high reliability, easy software control and maintenance.

Issues (problems)

• Synchronisation: all exchanges must be clock-locked; clock differences cause slips (lost or repeated frames).
• Delay: each time switch adds up to 125 µs; many in tandem add delay and need echo control.
• Codec per line: analogue subscriber lines need BORSCHT functions and a codec on each line card, which is costly.
• Jitter and wander on incoming links need elastic buffers.
• Control complexity: path search over slots and highways needs powerful processors and software.
• Interworking with analogue exchanges and signalling conversion.

Stored Program Control (SPC)

SPC is the control of a telephone exchange by a digital computer (processor) that runs a stored program, instead of hard-wired relays or electromechanical logic.

  [processor] <--> [program + data memory]
       |
  [scanners / distributors / signal units]
       |
  switching network  <-->  lines and trunks

• Scanners read the state of lines and trunks (off-hook, digits); the processor runs call-processing programs, consults the data memory (subscriber class, routing tables, charging) and orders the switching network through distributors/markers.
• Centralised SPC: one main processor (duplicated in standby, synchronous-duplex or load-sharing mode). Distributed SPC: many processors, each controlling part of the exchange or a set of functions.

Benefits: new services (call forwarding, waiting, conference, abbreviated dialling) by software change; easy changes of subscriber data and routing; automatic fault diagnosis and traffic statistics; centralised maintenance; accurate billing; faster call set-up; smaller size.

A time switch or Time Slot Interchanger (TSI) moves the speech sample (PCM byte) in one time slot of an incoming TDM frame into a different time slot of the outgoing frame. In sequential write, random read mode (also called output-associated control), samples are written into memory in order and read out in the order set by a control memory.

Main parts

• Speech (data) memory, SM: $c$ locations, one per time slot, each 8 bits wide (one PCM sample). For a 32-channel PCM frame, $c = 32$.
• Control (connection) memory, CM: $c$ locations, each holding an SM address ($\log_2 c$ bits, 5 bits for 32 slots).
• Time-slot counter: a modulo-$c$ counter driven by the channel clock. It gives the current slot number $0, 1, \dots, c-1$.
• Write/read control logic and the processor interface that loads the CM when a call is set up.

 Input TDM                              Output TDM
 frame                                  frame
 ----->+---------------------+--------->
       |   Speech memory     |
       |   (c x 8 bits)      |
       +---------------------+
   write addr ^          ^ read addr
 (sequential) |          | (random)
       +-------------+  +------------+
       | Time-slot   |->| Control    |
       | counter     |  | memory     |
       +-------------+  +------------+
                             ^
                     processor (call set-up)

Working principle

1. Write phase (sequential): in time slot $i$ of the incoming frame, the sample is written into SM location $i$. The write address comes straight from the time-slot counter, so SM fills in order 0, 1, 2, ... every frame.
2. Read phase (random): in output time slot $j$, the counter addresses CM location $j$. CM($j$) contains the SM address of the input slot that must go out in slot $j$. That SM location is read and placed in output slot $j$.
3. When a call is set up, the processor writes the input slot number into the CM location of the wanted output slot. When the call is released, the entry is cleared.
4. Each slot needs one write and one read, so in every slot time the memory is accessed twice.

Example

Connect input TS3 to output TS7 (32-slot frame):

• In TS3 the sample is written into SM(3).
• The processor has stored CM(7) = 3.
• In TS7 the logic reads CM(7) = 3, then reads SM(3) and sends it in output slot 7.
• The sample is delayed by $7 - 3 = 4$ slots. If the output slot comes before the input slot, the sample goes out in the next frame (delay up to one frame, 125 µs).

Timing limit

Frame time is 125 µs, so slot time is $125/c$ µs. Since there are two accesses per slot, the memory cycle time must satisfy

$$t_{access} \le \frac{125\ \mu s}{2c}$$

For $c = 32$: $t_{access} \le 1.95$ µs. Faster memory allows more channels per TSI.

Features

• Strictly non-blocking: any input slot can go to any free output slot.
• Gives a fixed delay of less than one frame per stage.
• Size is limited by memory speed, so large exchanges combine T stages with S stages (TST).
• Broadcasting is easy: several CM locations can hold the same SM address, so one input can feed several outputs.

An ST switch is a two-stage digital switch in which a space (S) stage is followed by a time (T) stage. The S stage is a time-multiplexed space switch that connects incoming TDM highways to outgoing highways; each outgoing highway has a time slot interchanger (TSI) that moves the sample to the required output slot.

 TDM in            S stage           T stage     TDM out
 I1 ------->+----------------+--->[TSI 1]---> O1
 I2 ------->|  time-shared   |--->[TSI 2]---> O2
 ..         |  crosspoint    |     ...         ..
 IN ------->|  matrix (N x N)|--->[TSI N]---> ON
            +----------------+
                  ^
            control memory (per output column)

Working: a sample arriving in slot $i$ on input highway $I_a$ must go to slot $j$ on output highway $O_b$. In slot $i$ the S-stage control memory closes crosspoint $(a,b)$, so the sample enters TSI $b$, which writes it and reads it out in slot $j$.

Drawback (blocking): the space stage must move the sample in the same time slot $i$ in which it arrives. If another call from a different input already uses slot $i$ to reach output highway $b$, the new call is blocked, even though slot $j$ on $O_b$ is free. There is only one path for each connection, so blocking is high under heavy load. TS switches have the same problem the other way round.

Remedy: add a third stage to get several alternative paths, giving STS or TST switches. The TST form is preferred in practice (e.g. in most large digital exchanges) because time expansion is cheaper than space expansion.

Stored Program Control (SPC) means that the exchange is controlled by a digital computer (processor) that runs a program stored in memory, instead of by hard-wired relay logic as in Strowger and crossbar exchanges. All digital exchanges use SPC.

What the program does

• Scans subscriber lines and trunks to detect off-hook, on-hook and digits.
• Analyses digits, finds a free path through the switching network and sets it up.
• Sends ringing, tones and signaling messages, and supervises the call.
• Records call data for charging (billing) and traffic statistics.
• Runs maintenance, fault diagnosis and administration tasks.

Types

• Centralised SPC: one main processor (usually duplicated for reliability) controls the whole exchange. Dual-processor modes are standby, synchronous duplex and load sharing.
• Distributed SPC: control is shared among many smaller processors (line-group processors, call processors, etc.). It is more reliable and easier to expand; most modern exchanges use it.

Advantages

• New services (call forwarding, call waiting, abbreviated dialling, conference calls) are added by changing software.
• Easy change of subscriber data and routing through a terminal.
• Automatic fault detection and remote maintenance.
• Fast call set-up and support for common channel signaling (SS7).
• Smaller size, lower power use and better reliability.

Disadvantages: high initial software cost, and a software fault can affect the whole exchange, so careful testing and processor redundancy are needed.

Working principle of a digital telephone exchange

A digital exchange switches speech as PCM samples (8-bit words, 8000 per second) using time-division techniques, under stored program control (SPC).

 Subscriber +-------+  +----------+  +-------+
 lines ---->| Line  |->| Digital  |->| Trunk |--> other
 (analog)   | units |<-| switching|<-| units |    exch.
            |BORSCHT|  | (TST)    |  |(E1)   |
            +-------+  +----------+  +-------+
                ^           ^            ^
            +-------------------------------+
            | Control processor (SPC)       |
            | + signaling                   |
            +-------------------------------+

1. Line unit: each analogue line has a line card doing the BORSCHT functions: Battery feed, Over-voltage protection, Ringing, Supervision, Coding (codec: A/D and D/A), Hybrid (2-wire to 4-wire), Testing.
2. Concentration and multiplexing: coded samples from many lines are multiplexed onto 32-channel (2.048 Mbps) PCM highways.
3. Digital switching network: time switches (TSIs) and space switches (usually in TST form) move each sample from its input slot and highway to the required output slot and highway.
4. Control: the processor detects off-hook, collects digits, finds a free path, writes the control memories of the T and S stages, sends ringing and tones, supervises and records charging data.
5. Trunk and signaling units: connect to other exchanges over E1 links; signaling is by CAS or CCS (SS7).

Crosspoints in a three-stage switch

Take $N$ inputs and $N$ outputs, divided into groups of $n$ lines, with $k$ middle-stage arrays.

• First stage: $N/n$ arrays, each $n \times k$
• Second stage: $k$ arrays, each $(N/n) \times (N/n)$
• Third stage: $N/n$ arrays, each $k \times n$

$$\begin{aligned} N_x &= \frac{N}{n}(nk) + k\left(\frac{N}{n}\right)^2 + \frac{N}{n}(kn) \\ &= 2Nk + k\left(\frac{N}{n}\right)^2 \end{aligned}$$

For a strictly non-blocking (Clos) network, $k = 2n - 1$:

$$N_x = (2n-1)\left[2N + \left(\frac{N}{n}\right)^2\right]$$

Example: $N = 100$, $n = 10$, $k = 2n-1 = 19$:

$$\begin{aligned} N_x &= 2(100)(19) + 19\left(\frac{100}{10}\right)^2 \\ &= 3800 + 1900 = 5700 \end{aligned}$$

A single-stage $100 \times 100$ switch needs $N^2 = 10\,000$ crosspoints, so the three-stage design saves 43% and is still non-blocking.

Answer: $N_x = 2Nk + k(N/n)^2$; for $N = 100$, $n = 10$, $k = 19$, $N_x = 5700$ crosspoints.

Blocking and non-blocking switching

• A blocking switch is one in which a call between a free input and a free output may still fail because no free internal path exists (internal links are busy with other calls). Multistage networks with too few middle-stage paths are blocking. Blocking probability is the chance that such a call is lost.
• A non-blocking switch is one in which any free input can always be connected to any free output, whatever other calls are in progress. A single-stage $N \times N$ crossbar is non-blocking but needs $N^2$ crosspoints.

Condition for a digital switch to be non-blocking

(a) Space-division three-stage (Clos) network. With $n$ inputs per first-stage array and $k$ middle arrays, the worst case is: the calling input's array already has $n-1$ busy inputs using $n-1$ different middle arrays, and the called output's array has $n-1$ busy outputs using $n-1$ other middle arrays. One more middle array is needed:

$$k \ge 2n - 1$$

(b) TST digital switch. Each incoming link has $c$ time slots, and the time-multiplexed space stage has $l$ internal time slots. By the same reasoning (with time slots in place of middle arrays):

$$l \ge 2c - 1$$

So a TST switch is non-blocking when the space stage runs at about twice the slot rate of the external links (time expansion).

(c) STS digital switch. With $N$ incoming TDM links and $k$ centre-stage TSIs: $k \ge 2N - 1$.

(d) Single time switch (TSI). It is always non-blocking provided the memory is fast enough: $t_{access} \le 125\ \mu s / 2c$.

Example

A TST switch has E1 links with $c = 32$ slots. For non-blocking operation, $l = 2(32) - 1 = 63$, so practical designs use 64 internal slots. With $l = 32$ only (no expansion), and link occupancy 0.9 E, blocking probability is

$$P_B = \left[1 - (1 - 0.9)^2\right]^{32} = 0.99^{32} \approx 0.725$$

Hence the time expansion to $l \ge 63$ is what makes the switch non-blocking.

For a space switch example: $N = 200$, $n = 10$ needs $k \ge 19$ middle arrays for non-blocking operation.

Blocking probability of multistage switches is found with Lee graphs: each path is drawn as links in series, parallel paths are independent, and each link is busy with probability $p'$.

STS switch

$N$ incoming TDM links enter an $N \times k$ space stage, then $k$ centre-stage TSIs, then a $k \times N$ space stage.

 A o---(k parallel paths, each = 2 links)---o B
        input S -> TSI_i -> output S

• Each path uses two internal links in series: input S → TSI and TSI → output S.
• If $p$ is the occupancy of external links, the internal link occupancy is

$$p' = \frac{p}{\beta}, \quad \beta = \frac{k}{N} \text{ (space expansion)}$$

• A path is free only if both links are free: probability $(1-p')^2$. Path busy: $1-(1-p')^2$.
• There are $k$ parallel paths (one per centre TSI); the call is blocked only if all are busy:

$$P_{B,STS} = \left[1 - (1 - p')^2\right]^{k}$$

TST switch

$N$ incoming links, each with $c$ slots, go to input TSIs; a time-multiplexed space stage with $l$ internal time slots; then output TSIs.

• The alternative paths are the $l$ internal time slots of the space stage. Each path uses two links: input TSI → S (in slot $x$) and S → output TSI (in slot $x$).
• Internal link occupancy:

$$p' = \frac{p}{\alpha}, \quad \alpha = \frac{l}{c} \text{ (time expansion)}$$

• Same Lee graph with $l$ parallel paths:

$$P_{B,TST} = \left[1 - (1 - p')^2\right]^{l}$$

Why TST has lower blocking

The expressions have the same form; the blocking depends on the number of parallel paths (the exponent) and $p'$.

1. In STS the exponent is $k$, the number of centre TSIs. Each extra path needs a whole TSI and adds crosspoints to both space stages ($2Nk$), so $k$ stays small.
2. In TST the exponent is $l$, the number of internal time slots. It is equal to or greater than the frame size $c$ (32 to 1024 in practice) and is raised just by running the space stage and memories faster, which is cheap.
3. So for a practical size, $l \gg k$ and the TST result is far smaller.

Example: $p = 0.7$ E, no expansion ($p' = 0.7$), $1-(1-0.7)^2 = 0.91$:

• STS with $N = k = 16$ links: $P_B = 0.91^{16} = 0.221$
• TST with $c = l = 32$ slots: $P_B = 0.91^{32} = 0.0489$
• TST with time expansion $l = 64$ ($p' = 0.35$): $P_B = 0.5775^{64} \approx 5.5 \times 10^{-16}$

Hence TST gives lower blocking at lower cost, which is why large digital exchanges use TST (or TSST/TSSST) structures.

Given: time slots per frame on the external (secondary multiplex) link, $c = 120$; occupancy $p = 0.6$ E and $0.9$ E.

Non-blocking condition

A TST switch is strictly non-blocking when the number of space-stage time slots satisfies $l \ge 2c - 1$:

$$l = 2(120) - 1 = 239 \text{ time slots}$$

Blocking probability

Lee-graph formula for TST:

$$P_B = \left[1 - (1 - p')^2\right]^{l}, \qquad p' = \frac{p\,c}{l}$$

Step 1: internal link occupancy $p'$

Step 2: path-busy probability $q = 1 - (1-p')^2$

Step 3: $P_B = q^{\,l}$

For example, $l = 120$, $p = 0.9$:

$$P_B = 0.99^{120} = 0.299$$

and $l = 150$, $p = 0.6$:

$$P_B = 0.7296^{150} = 2.90 \times 10^{-21}$$

Comment: even without time expansion ($l = 120$) the blocking is negligible at 0.6 E, but at 0.9 E it is about 30%. A modest time expansion (150 or 200 slots) brings it down to a negligible value, far fewer than the 239 slots needed for strictly non-blocking operation.

Answer: $l = 239$ slots for non-blocking; $P_B$ = $8.19 \times 10^{-10}$, $2.90 \times 10^{-21}$, $1.70 \times 10^{-46}$ (0.6 E) and $0.299$, $4.80 \times 10^{-6}$, $2.24 \times 10^{-21}$ (0.9 E) for $l$ = 120, 150, 200.

Three-stage network with $N$ lines, groups of $n$, and $k$ middle arrays:

• Stage 1: $N/n$ arrays of $n \times k$
• Stage 2: $k$ arrays of $(N/n) \times (N/n)$
• Stage 3: $N/n$ arrays of $k \times n$

$$N_x = 2Nk + k\left(\frac{N}{n}\right)^2$$

Design 1: $N = 200$, $n = 20$, $k = 4$

Number of groups $N/n = 200/20 = 10$.

$$N_x = 2(200)(4) + 4(10)^2 = 1600 + 400 = 2000$$

 20 in  [20x4] \                   / [4x20] 20 out
 20 in  [20x4] -->  4 x [10x10] -->  [4x20] 20 out
  ...     ...  /     middle      \    ...
 20 in  [20x4]  (10 arrays)          [4x20] 20 out

Each first-stage array has one link to each middle array; each middle array has one link to each third-stage array.

This needs only 5% of the $200^2 = 40\,000$ crosspoints of a single-stage switch, but only 4 of the 20 inputs of a group can be connected at once, so it is a blocking (concentrating) design, since $k = 4 < 2n - 1 = 39$.

Design 2: Clos non-blocking with minimum crosspoints

For strict non-blocking, $k = 2n - 1$. Crosspoints are minimum when

$$n = \sqrt{\frac{N}{2}} = \sqrt{\frac{200}{2}} = 10$$ $$k = 2n - 1 = 19, \qquad \frac{N}{n} = \frac{200}{10} = 20$$

Check with the Clos minimum formula:

$$\begin{aligned} N_{x,min} &= 4N\left(\sqrt{2N} - 1\right) \\ &= 4(200)\left(\sqrt{400} - 1\right) = 800 \times 19 = 15\,200 \end{aligned}$$

Answer: Design 1 needs 2000 crosspoints (blocking). The Clos design ($n = 10$, $k = 19$, 20 outer arrays) needs 15 200 crosspoints and is strictly non-blocking, which is 38% of a 40 000-crosspoint single-stage switch.

Multistage switching

Multistage switching builds a large switch from several stages of smaller switches connected by internal links, instead of one big $N \times N$ matrix. It cuts the number of crosspoints (or memory) needed, and gives several alternative paths for each call. The cost is a small chance of internal blocking unless enough paths are provided. Examples: three-stage space networks, STS, TST, TSST.

TST switching

A Time–Space–Time switch has an input time stage, a time-multiplexed space stage and an output time stage.

 Link 1 -->[TSI-A1]--+-----------+--[TSI-B1]--> Link 1
 Link 2 -->[TSI-A2]--| N x N     |--[TSI-B2]--> Link 2
   ...        ...    | space     |     ...
 Link N -->[TSI-AN]--| (TMS)     |--[TSI-BN]--> Link N
                     +-----------+
  c slots   in T      l internal    out T    c slots
                       slots

Working (example): connect slot 5 of link 1 to slot 20 of link N.

1. The control processor searches for an internal slot $x$ that is free both on the output of TSI-A1 and on the input of TSI-BN (say $x = 12$).
2. Input T stage: TSI-A1 moves the sample from slot 5 to slot 12.
3. Space stage: in slot 12 its control memory closes crosspoint (1, N), so the sample passes from highway 1 to highway N.
4. Output T stage: TSI-BN moves the sample from slot 12 to slot 20.
5. The return direction uses another slot, often $x + l/2$ (mod $l$), so one search serves both directions.

Since any internal slot $x$ can be used, there are $l$ alternative paths.

Blocking probability

Using a Lee graph: each path has two internal links in series (TSI-A → S and S → TSI-B), and there are $l$ paths in parallel. With external occupancy $p$ and time expansion $\alpha = l/c$, the internal link occupancy is $p' = p/\alpha$:

$$P_B = \left[1 - (1 - p')^2\right]^{l}$$

• Non-blocking when $l \ge 2c - 1$.
• Example: $c = l = 32$, $p = 0.6$: $P_B = [1 - 0.4^2]^{32} = 0.84^{32} \approx 3.8 \times 10^{-3}$.

Why it is preferred: time expansion is cheap (faster memory), the space stage is small, and the blocking is very low, so TST (and TSST) is used in most large digital exchanges.

Stored program control

Stored Program Control (SPC) is the control of an exchange by a processor running programs stored in memory. Call processing, routing, charging and maintenance are done in software, so new features can be added by changing the program.

Dual-processor architecture in centralised SPC

In centralised SPC one processor controls the whole exchange, so a failure would stop all calls. The processor is therefore duplicated. The two processors (P1 and P2) share or copy the memory and work in one of three modes.

  +------+   +------+
  |  P1  |   |  P2  |
  +--+---+   +---+--+
     |  +----+   |
     +--|Comp|---+     (comparator in
     |  +----+   |      sync duplex)
  +--+---+   +---+--+
  |  M1  |   |  M2  |   (memories)
  +------+   +------+
        \     /
     exchange hardware

1. Standby mode

• One processor is active; the other is idle on standby.
• The standby takes over when the active one fails.
• The memory is shared or the active processor regularly copies its data to a secondary store, so the standby can reload the current call data.
• Simple, but calls being set up at the time of failure may be lost.

2. Synchronous duplex mode

• Both processors run the same program at the same time, each with its own memory, and get the same inputs.
• A comparator checks their outputs after each step. If they agree, normal working continues.
• On a mismatch, both run diagnostic programs; the faulty one is taken out of service and the healthy one continues alone.
• Gives fast fault detection and no loss of calls, but transient faults may cause needless check routines.

3. Load-sharing mode

• Each processor handles part of the traffic (e.g. calls are given to them alternately or at random).
• They share a common memory and use an exclusion device (ED) so both do not seize the same resource at once.
• If one fails, the other carries the full load (with possible reduced grade of service at the busy hour).
• Gives higher call-handling capacity than standby or synchronous modes.

Availability

For one processor, $A = \dfrac{MTBF}{MTBF + MTTR}$. For a dual system the mean time between system failures becomes

$$MTBF_D = \frac{MTBF^2}{2\,MTTR}$$

so unavailability falls from about $MTTR/MTBF$ to about $2\,MTTR^2/MTBF^2$. This large gain is why all centralised SPC exchanges use duplicated processors.

A time switch or TSI (Time Slot Interchanger) changes the time slot of a PCM sample within a TDM frame. In the sequential read, random write mode (also called input-associated control), the address at which each incoming sample is written is chosen by a control memory, and the speech memory is read out in order.

Main parts

• Speech memory (SM): $c$ words of 8 bits, one per time slot.
• Control memory (CM): $c$ words of $\log_2 c$ bits. CM($i$) holds the SM address where the sample of input slot $i$ must be written.
• Time-slot counter: a modulo-$c$ counter giving the current slot number.
• Processor interface: loads CM entries when calls are set up or released.

 Input TDM                              Output TDM
 --------->+---------------------+---------->
           |   Speech memory     |
           |   (c x 8 bits)      |
           +---------------------+
  write addr ^             ^ read addr
   (random)  |             | (sequential)
      +------------+  +-------------+
      | Control    |<-| Time-slot   |
      | memory     |  | counter     |
      +------------+  +-------------+
           ^
   processor (call set-up)

Working principle

1. Write phase (random): in input slot $i$, the counter addresses CM($i$). The value stored there, say $j$, is used as the write address, so the sample is stored in SM($j$).
2. Read phase (sequential): the counter also gives the read address directly. In output slot $j$, SM($j$) is read and sent out. So a sample written into SM($j$) leaves in output slot $j$.
3. To set up a call from input slot $i$ to output slot $j$, the processor writes $j$ into CM($i$).
4. One write and one read happen in every slot.

Example

Connect input TS2 to output TS9 in a 32-slot frame:

• Processor sets CM(2) = 9.
• In TS2 the sample is written into SM(9).
• In TS9 the counter reads SM(9), so the sample appears in output slot 9.
• Delay = $9 - 2 = 7$ slots $= 7 \times 3.9 \approx 27.3$ µs.

Timing

Slot time = $125/c$ µs and two memory accesses per slot are needed:

$$t_{access} \le \frac{125\ \mu s}{2c}$$

For 32 channels this is 1.95 µs. Maximum channels for a memory of access time $t$: $c_{max} = 125\ \mu s / 2t$.

Features

• Strictly non-blocking for its own frame.
• Delay is less than one frame (125 µs).
• Broadcast is not possible in this mode, because one input sample is written into only one SM location. (In sequential-write, random-read mode, several outputs can read the same location.)
• Useful at the input side of a TST switch, where each input slot has a fixed control entry.

A three-stage network is strictly non-blocking if a free input can always be connected to a free output, however the existing calls are routed. The condition was derived by C. Clos (1953).

Network

• $N$ inputs and $N$ outputs; groups of $n$ lines.
• Stage 1: $N/n$ arrays of $n \times k$; Stage 2: $k$ arrays of $(N/n) \times (N/n)$; Stage 3: $N/n$ arrays of $k \times n$.
• Each first-stage array has one link to every middle array; each middle array has one link to every third-stage array.

  input array A          output array B
  (n inputs)             (n outputs)
  n-1 busy -> use        n-1 busy -> use
  n-1 middle arrays      n-1 other middle
       \                      /
        \  need 1 more free  /
         +-- middle array --+
     total k >= (n-1)+(n-1)+1

Derivation of $k \ge 2n - 1$

Consider a new call from a free input of first-stage array A to a free output of third-stage array B. Take the worst case:

1. Array A has $n$ inputs; the other $n - 1$ are busy. Each of those calls uses a different link from A, so they occupy $n - 1$ middle arrays.
2. Array B has $n$ outputs; the other $n - 1$ are busy, using $n - 1$ middle arrays.
3. In the worst case, these two sets of middle arrays are all different, so $2(n - 1)$ middle arrays cannot be used.
4. To connect A to B, at least one more middle array must be free:

$$k \ge (n - 1) + (n - 1) + 1 = 2n - 1$$

This is the necessary and sufficient condition for strict non-blocking.

Crosspoints and optimum $n$

$$N_x = 2Nk + k\left(\frac{N}{n}\right)^2 = (2n-1)\left[2N + \frac{N^2}{n^2}\right]$$

Differentiating and treating $2n - 1 \approx 2n$ for large $n$:

$$\begin{aligned} \frac{dN_x}{dn} &= 4N + N^2\frac{2 - 2n}{n^3} \approx 4N - \frac{2N^2}{n^2} = 0 \\ n_{opt} &= \sqrt{\frac{N}{2}} \end{aligned}$$

Substituting:

$$N_{x,min} = 4N\left(\sqrt{2N} - 1\right)$$

Example

$N = 200$: $n = 10$, $k = 19$, $N_{x,min} = 4(200)(20 - 1) = 15\,200$, compared with $N^2 = 40\,000$ for a single-stage switch.

The same idea applies to digital switches: a TST switch is strictly non-blocking when the internal time slots satisfy $l \ge 2c - 1$, and an STS switch when the centre TSIs satisfy $k \ge 2N - 1$.

A TSI has a speech memory (SM) holding one PCM sample per time slot and a control memory (CM) set by the processor. The two modes differ in which access (write or read) the CM controls.

Sequential write, random read (output-associated control)

• Input sample in slot $i$ is written into SM($i$), using the time-slot counter as address.
• In output slot $j$, CM($j$) gives the SM address to read; the sample of that input slot is sent out.
• To connect input $i$ to output $j$: set CM($j$) = $i$.

Random write, sequential read (input-associated control)

• In input slot $i$, CM($i$) gives the SM address $j$ where the sample is written.
• SM is read in order, so SM($j$) goes out in output slot $j$.
• To connect input $i$ to output $j$: set CM($i$) = $j$.

 SW-RR:  in --> SM[counter]      SM[CM[counter]] --> out
 RW-SR:  in --> SM[CM[counter]]  SM[counter]     --> out

Example: input TS4 to output TS10. SW-RR: sample stored in SM(4), CM(10) = 4. RW-SR: CM(4) = 10, sample stored in SM(10). Output is the same in both.

Both modes need the same memory size ($c \times 8$ bits SM, $c \times \log_2 c$ bits CM) and are non-blocking for one frame; they are often used together in a TST switch so that one control memory word can serve both directions.

Difference between TST and STS switches

Three-stage design

Reading of the data: the first stage has 4 arrays with 5 input lines each, so $N = 4 \times 5 = 20$ lines, $n = 5$; the second stage has $k = 6$ arrays.

• Stage 1: 4 arrays of $5 \times 6$
• Stage 2: 6 arrays of $4 \times 4$ (each middle array has one link from each of the 4 first-stage arrays)
• Stage 3: 4 arrays of $6 \times 5$

  5 in [5x6] \           / [6x5] 5 out
  5 in [5x6] --> 6 x [4x4] --> [6x5] 5 out
  5 in [5x6] -->  middle  --> [6x5] 5 out
  5 in [5x6] /           \ [6x5] 5 out
  (20 inputs)               (20 outputs)

Crosspoints

$$\begin{aligned} N_1 &= 4 \times (5 \times 6) = 120 \\ N_2 &= 6 \times (4 \times 4) = 96 \\ N_3 &= 4 \times (6 \times 5) = 120 \\ N_x &= 120 + 96 + 120 = 336 \end{aligned}$$

Check: $N_x = 2Nk + k(N/n)^2 = 2(20)(6) + 6(4)^2 = 240 + 96 = 336$.

A single-stage $20 \times 20$ switch needs 400 crosspoints, so the saving is 64 crosspoints (16%). Since $k = 6 < 2n - 1 = 9$, this network is blocking; 9 middle arrays would be needed for strict non-blocking.

Answer: total crosspoints = 336.

Technical structure of a telephone exchange

A telephone exchange connects any subscriber line or trunk to any other on demand. It has the following main subsystems:

 Subscribers                         Other exchanges
   |                                       ^
 +------------+  +-------------+  +-------------+
 | Subscriber |->|  Switching  |->|  Trunk /    |
 | line units |<-|  network    |<-|  junction   |
 | (BORSCHT)  |  |  (T, S, TST)|  |  interface  |
 +------------+  +-------------+  +-------------+
      ^   ^             ^             ^
      |   +--------+    |    +--------+
      |   | Signal-|    |    |
      |   | ling   |<-->+<-->|  Control (SPC
      |   +--------+         |  processors)
      +--------------------> +---------------+
               O&M: charging, testing, admin

1. Subscriber line interface: each line card does BORSCHT (battery feed, over-voltage protection, ringing, supervision, codec, hybrid, testing). Line concentrators combine many lightly used lines onto fewer switch ports.
2. Switching network: makes the speech path. In digital exchanges it is a TST (or TSST) network of time switches and space switches.
3. Trunk/junction interface: connects to other exchanges on E1 (2.048 Mbps) PCM links, with frame alignment and clock synchronisation.
4. Signaling equipment: subscriber signaling (dial tone, DTMF receivers, ringing, busy tone) and inter-exchange signaling (CAS or CCS/SS7).
5. Control unit: SPC processors that detect calls, analyse digits, find paths, set the switch, supervise calls and release them.
6. Operation and maintenance: charging (billing) records, traffic measurement, alarms, testing and subscriber administration.
7. Power and synchronisation: 48 V DC battery plant and a master clock.

Comparison of TST and STS switches

TST is preferred in practice because, for the same blocking, it needs less hardware and its paths are easy to find by searching time slots.

Assumptions: each 5-bit connection-memory word is a one-hot select for the decode logic, with the bits in the order I1 I2 I3 I4 I5 (left to right). Channel 1 of each trunk arrives first (in $t_0$), channel 2 in $t_1$, and so on, as the channels are written right-to-left ("A4 A3 A2 A1").

Design of the space switch

This is a time-multiplexed space switch with 5 input trunks (rows) and 4 output trunks (columns), with 4 time slots per frame.

          O1    O2    O3    O4
 I1 ----- x --- x --- x --- x
 I2 ----- x --- x --- x --- x
 I3 ----- x --- x --- x --- x
 I4 ----- x --- x --- x --- x
 I5 ----- x --- x --- x --- x
          |     |     |     |
       [CM1] [CM2] [CM3] [CM4]
       decode logic per column
       (4 words x 5 bits each)

• Each output column has its own control memory with 4 words (one per time slot) of 5 bits.
• In each time slot the decoder of a column closes the one crosspoint whose bit is 1, connecting that input trunk to the output trunk for that slot only.
• The switch has $5 \times 4 = 20$ crosspoints and $4 \times 4 = 16$ control words.

Number of virtual paths

Each crosspoint can carry a different connection in each time slot:

$$\text{virtual paths} = 5 \times 4 \times 4 = 80$$

In each time slot at most 4 connections exist (one per output), so in one frame at most $4 \times 4 = 16$ of these paths are in use; the given memory uses all 16.

Decoding the connection memory

Output channels in $t_0$ to $t_3$

Written in the same style as the input trunks (latest on the left):

• O1: B4 E3 A2 C1
• O2: A4 D3 C2 B1
• O3: D4 C3 B2 A1
• O4: C4 A3 E2 D1

A space switch does not change the time slot of a sample: channel $m$ always leaves in time slot $t_{m-1}$. Changing slots needs a time switch, which is why practical exchanges use TST.