Positive/negative logic; XNOR using NAND

Positive and negative logic

• Positive logic: HIGH voltage = logic 1, LOW voltage = logic 0 (e.g. TTL: +5 V = 1, 0 V = 0).
• Negative logic: HIGH voltage = logic 0, LOW voltage = logic 1 (e.g. +5 V = 0, 0 V = 1).

The same physical gate performs a different logic function in the two systems, because changing the convention complements every input and output. Example: a gate whose output is HIGH only when both inputs are HIGH is an AND gate in positive logic but an OR gate in negative logic.

XNOR using NAND gates only

$Y = A \odot B = \overline{A \oplus B}$. First build XOR with 4 NAND gates, then invert it with a fifth NAND gate whose two inputs are tied together ($\overline{X \cdot X} = \bar X$). Minimum: 5 NAND gates.

$$\begin{aligned} G_1 &= \overline{AB} \\ G_2 &= \overline{A G_1} \\ G_3 &= \overline{B G_1} \\ G_4 &= \overline{G_2 G_3} = A \oplus B \\ Y &= \overline{G_4 \cdot G_4} = \overline{A \oplus B} = AB + \bar A \bar B \end{aligned}$$

 A --+-----------[NAND G2]--+
     |              |       |
     +--[NAND G1]---+       +--[NAND G4]--+--[NAND G5]-- Y
     |              |       |             +--|
 B --+-----------[NAND G3]--+       (inputs tied: NOT)

Y is 1 when both inputs are equal, which is XNOR.