Types of registers

A register is a group of flip-flops (usually D type) with a common clock that stores a binary word; an n-bit register has n flip-flops. A shift register can also move the stored bits left or right at each clock. Registers are classified by how data is entered and taken out.

1. Serial In Serial Out (SISO)

Data enters one bit per clock at FF-A and leaves one bit per clock from FF-D.

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-->|D  QB|-->|D  QC|-->|D  QD|--> Dout
      |>    |   |>    |   |>    |   |>    |
      +-----+   +-----+   +-----+   +-----+
         ^         ^         ^         ^
 CLK ----+---------+---------+---------+

A 4-bit SISO takes 4 clocks to load and 4 to empty; used as a delay line.

2. Serial In Parallel Out (SIPO)

Data enters serially; after n clocks all bits are read at once from QA to QD.

 Din  +-----+   +-----+   +-----+   +-----+
 ---->|D  QA|-+>|D  QB|-+>|D  QC|-+>|D  QD|-+
      |>    | | |>    | | |>    | | |>    | |
      +-----+ | +-----+ | +-----+ | +-----+ |
         ^    |    ^    |    ^    |    ^    |
 CLK ----+----|----+----|----+----|----+    |
              v         v         v         v
             QA        QB        QC        QD
          (parallel outputs read together)

Used for serial-to-parallel conversion (e.g. serial receiver).

3. Parallel In Serial Out (PISO)

All bits are loaded together when SH/LD' = 0; with SH/LD' = 1 they are shifted out one per clock at QD.

       PA          PB          PC          PD
       |           |           |           |
    +-----+     +-----+     +-----+     +-----+
 0->| MUX | +-->| MUX | +-->| MUX | +-->| MUX |
    +-----+ |   +-----+ |   +-----+ |   +-----+
       |    |      |    |      |    |      |
    +-----+ |   +-----+ |   +-----+ |   +-----+
    |D  QA|-+   |D  QB|-+   |D  QC|-+   |D  QD|-->
    |>    |     |>    |     |>    |     |>    | Serial
    +-----+     +-----+     +-----+     +-----+  out
 MUX = 2 AND + 1 OR: D = SH.(Q of left FF) + SH'.P
 SH/LD' and CLK are common to all stages.

Used for parallel-to-serial conversion (e.g. serial transmitter).

4. Parallel In Parallel Out (PIPO)

Each flip-flop has its own input and output; at one clock edge the whole word is stored and is immediately available. There is no shifting.

     PA        PB        PC        PD
     |         |         |         |
  +-----+   +-----+   +-----+   +-----+
  |D    |   |D    |   |D    |   |D    |
  |>   Q|   |>   Q|   |>   Q|   |>   Q|
  +-----+   +-----+   +-----+   +-----+
   ^  |      ^  |      ^  |      ^  |
 CLK  QA       QB        QC        QD
 (common clock; no connection between stages)

Used as a storage (buffer) register, e.g. accumulator or latch for data.

5. Bidirectional and universal shift registers

• Bidirectional: a control line (RIGHT/LEFT') selects shifting right ($D_B = Q_A$) or left ($D_B = Q_C$) through AND-OR gates.
• Universal (e.g. IC 74194): can hold, shift right, shift left and parallel load, selected by mode inputs S1 S0 (00 hold, 01 shift right, 10 shift left, 11 load).