- Asked 2/13
- 2072 Chaitra · 3+4 marks
- 2071 Shrawan · 3+4 marks
Square root circuit and √((V1V2)²+(V3V4)²)
Short answer
Use a log amp, an inverting stage of gain -1/2, and an antilog amp so V0 = exp(0.5 ln Vi) = sqrt(Vi). For V0 = sqrt((V1V2)^2 + (V3V4)^2), form each square with log-antilog stages, sum them, then pass the sum through a square-root block. Inputs must be positive.
Construct a circuit that generates square root of an input voltage and derive its input-output relationship. Draw a circuit that produces the output voltage V0 = √((V1·V2)² + (V3·V4)²).
Square-root circuit
Taking a square root means multiplying the logarithm by ½: √Vi = exp(½ ln Vi).
Building blocks used (all voltages in volts, Vref = 1 V, K = scale factor such as VT or 1 V/decade):
- Log amp (L): output = −K ln(Vin), for Vin > 0
- Antilog amp (E): output = exp(Vin/K)
- Inverting amp of gain −m: output = −m × input
R/2
+---/\/\/---+
| |
Vi -> [LOG] --V1'--[R]---+--(-)\ |
>---+--> V2'
GND--(+)/
V2' -> [ANTILOG] -> Vo
Derivation:
- Log amp: V1' = −K ln Vi
- Inverting amplifier with gain −(R/2)/R = −½:
V2' = −½ × (−K ln Vi) = (K/2) ln Vi
- Antilog amp:
Vo = exp(V2'/K) = exp(½ ln Vi) = Vi^(1/2)
Result: Vo = √Vi. With a general reference, Vo = √(Vref·Vi). For example, Vi = 9 V gives Vo = 3 V (Vref = 1 V). The input must be positive.
Circuit for V0 = √((V1·V2)² + (V3·V4)²)
Plan: form (V1V2)² and (V3V4)² with log–antilog stages, add them, then take the square root.
V1->[LOG]-+
+->[summer, gain -2]->[ANTILOG]->(V1V2)^2 -+
V2->[LOG]-+ |
[SUMMER] <----+
V3->[LOG]-+ ^ |
+->[summer, gain -2]->[ANTILOG]+ | S
V4->[LOG]-+ (V3V4)^2 v
S -> [LOG] -> [gain -1/2] -> [ANTILOG] -> V0
Step by step:
- Log amps give −K ln V1, −K ln V2, −K ln V3 and −K ln V4.
- Inverting summer with gain 2 (input resistors R, feedback 2R):
Va = −2(−K ln V1 − K ln V2) = 2K ln(V1V2)
The antilog gives exp(Va/K) = (V1V2)². In the same way the second branch gives (V3V4)².
- A non-inverting summer (or an inverting summer followed by an inverter) gives:
S = (V1V2)² + (V3V4)²
- The square-root block (log, gain −½, antilog) gives:
V0 = √S = √( (V1V2)² + (V3V4)² )
All inputs must be positive (or first passed through precision rectifiers, since the result depends only on squares). The circuit uses 8 log or antilog amps (5 log, 3 antilog) plus the summing and scaling op-amps.
✓ Answer checked by Claude Opus 5.5 (high effort)
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