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Address sequencing capabilities of control memory

Short answer

The sequencer must increment CAR, branch unconditionally, branch conditionally on status bits, map opcode to routine start address, support subroutine call/return with SBR, and load initial fetch address. A multiplexer selects between CAR+1, the AD field, SBR, or mapping logic based on CD and BR fields.

Explain the address sequencing capabilities required in a control memory.

The control memory holds microprograms made of routines. The address sequencing hardware must be able to do the following.

  1. Incrementing the control address register: after each microinstruction, CAR ← CAR + 1 to follow the routine in sequence.
  2. Unconditional branch: load CAR with the branch address from the AD field (BR = JMP, CD = U).
  3. Conditional branch: test a status bit (I, S, Z, carry); if true, CAR ← AD, else CAR ← CAR + 1. This gives decisions in the microprogram.
  4. Mapping of instruction: the opcode of the machine instruction is converted into the starting address of its routine in the control memory (for a 4-bit opcode: 0 xxxx 00).
  5. Subroutine call and return: CALL stores the return address (CAR + 1) in the subroutine register (SBR) and branches; RET loads CAR from SBR. Common routines (like indirect address calculation) can be shared.
  6. Initial address: on reset, CAR loads the address of the first microinstruction (the fetch routine).

A multiplexer selects among CAR + 1, the AD field, SBR and the mapping logic under control of the CD and BR fields.

✓ Answer checked by Claude Opus 5.5 (high effort)

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