Skip to main content

Design of a 2-bit ALU

Short answer

Two 1-bit slices each with AND, OR, full adder and 4×1 MUX. S1S0=00 for AND, 01 for OR, 10 for ADD (carry chain). Slice 0 takes Cin=0, output F0 and carry to slice 1. Common S1,S0 select operation for both bits.

Design a 2-bit ALU that can perform addition, AND and OR operations.

A 2-bit ALU is two identical 1-bit slices in cascade. Each slice has a full adder (ADD), an AND gate, an OR gate and a 4×1 multiplexer that selects the result.

S1 S0Operation
0 0Fi = Ai AND Bi
0 1Fi = Ai OR Bi
1 0Fi = Ai + Bi + Ci (add)
1 1Not used (spare MUX input)
   Ai  Bi
    |   |
    +---+------+--------+
    |   |      |        |
 +--v-+ +v---+ +v-------v-+
 | AND| | OR | |Full adder|<-- Ci
 +--+-+ +-+--+ +----+-----+--> Ci+1
    |0    |1        |2
 +--v-----v---------v--+
 |  MUX 4x1 (S1 S0)    |
 +----------+----------+
            v
            Fi
  • Slice 0: inputs A0, B0, C0 (= 0 for add). Output F0, carry C1.
  • Slice 1: inputs A1, B1, C1. Output F1, carry C2 (carry-out).
  • Full-adder equations: Sum_i = Ai ⊕ Bi ⊕ Ci, Ci+1 = AiBi + Ci(Ai ⊕ Bi).
  • S1 and S0 are common to both slices, so one control word selects the same operation for both bits.

✓ Answer checked by Claude Opus 5.5 (high effort)

Related questions

All Computer Organization and Architecture chapter 5 questions →