ALU design with 2-bit ALU

An ALU is a combinational circuit that performs arithmetic and logic microoperations on n-bit operands. It is designed as n identical 1-bit slices connected in cascade.

Stages of ALU design

1. Specify the operations, word length and control inputs (here: add, subtract, AND, OR and XOR on 2 bits).
2. Partition the ALU into an arithmetic unit, a logic unit and an output selector (multiplexer).
3. Design one bit slice: a full adder with a B-complementer (XOR gate) for add/subtract, AND, OR and XOR gates for the logic unit, and a 4×1 MUX to choose the result.
4. Cascade the slices: the carry-out of bit 0 goes to the carry-in of bit 1. Add status flags (carry, zero, sign, overflow).
5. Verify the design with a function table and test inputs.

Function table

Select lines S1 S0 and mode M (for arithmetic, M = 0 means add and M = 1 means subtract; the carry-in of bit 0 = M):

One-bit slice

           Ai   Bi
            |    |
            |    +------------------+
            |    |                  |
   +--------+----+--------+         v
   |        |    |        |     [ XOR ]<--- M
   v        v    v        |        | Bi' = Bi xor M
 [AND]    [OR]  [XOR]     | Ai     v
   |        |    |        +--> [ Full adder ]<--- Ci
   |        |    |               |        |
   |        |    |               | Si     +---> Ci+1 (to next slice)
   v        v    v               v
 +------------------------------------+
 | 4 x 1 MUX (select S1 S0)           |
 | 00: AND  01: OR  10: XOR  11: Si   |
 +-----------------+------------------+
                   v
                   Fi

• The AND, OR and XOR gates each take Ai and the original Bi; only the full adder uses Bi'.
• Bi' = Bi XOR M, so a subtraction uses the 2's complement of B (B is inverted and C0 = 1).
• Sum Si = Ai ⊕ Bi' ⊕ Ci and carry Ci+1 = Ai·Bi' + Ci(Ai ⊕ Bi').

2-bit ALU

   A1 B1                A0 B0
    |  |                 |  |
 +--v--v--+  C1       +--v--v--+  C0 = M
 | slice 1 |<---------| slice 0 |<--- M
 +----+----+          +----+----+
      |  C2 (carry out)     |
      v                     v
      F1                    F0
   (all slices share S1, S0, M)

The same S1, S0 and M lines go to both slices. Slice 0 produces F0 and the carry C1; slice 1 uses C1 and produces F1 and the carry-out C2. For example, A = 11 and B = 01 with S1S0 = 11 and M = 0 give F = 00 and C2 = 1 (3 + 1 = 4); with M = 1 they give F = 10 (3 − 1 = 2).