DMA active and idle cycles

In a DMA system the bus is used by either the CPU or the DMA controller (DMAC), so operation alternates between idle and active cycles.

• Idle cycle: the DMAC has no request (no DREQ) or has no bus. The CPU owns the bus and executes its program. The DMAC only samples DREQ lines.
• Active cycle: after DREQ, the DMAC sends HOLD, receives HLDA, and then controls the buses. It transfers one byte (cycle stealing), a block (burst) or until the CPU needs the bus. After the transfer, HOLD is released and the CPU resumes.

 Time ->
 CPU bus : |CPU CPU CPU|          |CPU CPU CPU|
 DMAC    :             |DMA DMA DMA|
 HOLD    : ____________|-----------|____________
 HLDA    : _____________|----------|____________
          idle cycle    active cycle   idle cycle

The states of the 8237: SI (idle), S0 (wait for HLDA), S1-S4 (transfer), SW (wait).

Disadvantages of DMA controllers

1. Extra hardware (DMA controller, bus arbitration logic) increases cost and complexity.
2. Programming the controller (address, count, mode) is more complex.
3. The CPU is stopped from using the bus during DMA (bus contention), so its throughput is reduced; in burst mode interrupts may be delayed.
4. Not efficient for small or slow transfers because of set-up overhead.
5. Memory and bus must be fast enough to support the DMA rate.
6. Errors or an erroneous address/count can overwrite memory and are hard to debug.
7. Cache coherence problems appear in systems with cache.