Low power design reasons and guidelines

Reasons for low power design

1. Battery life: portable and handheld devices (phones, sensors, wearables) need to run for a long time on small batteries.
2. Heat reduction: less power means less heating, so smaller heat sinks, no fans, smaller size and better reliability (failure rate rises with temperature).
3. Lower cost of supplies, batteries and cooling; lower running energy cost.
4. Reliability and noise: low current gives less supply noise and less EMI.
5. Environment and regulation: energy-saving standards, remote or solar-powered systems.
6. Packaging density: more circuits in smaller packages.

Guidelines

1. Use a low supply voltage: CMOS dynamic power P = C·V²·f falls with the square of V, so use 3.3 V or 1.8 V devices.
2. Reduce the clock frequency to the lowest value that meets the speed need; use clock gating.
3. Use sleep/idle/power-down modes and wake only on events/interrupts; shut off unused peripherals.
4. Choose low-power components: CMOS logic, low-power MCU, low-quiescent-current regulators (LDO or efficient switching regulators), micro-power op-amps.
5. Minimise the capacitance being switched: short traces, fewer loads, reduce the activity of nodes (fewer toggles).
6. Avoid static current: no pull-up resistors left conducting, high-value resistors where possible, unused inputs tied to defined levels (floating CMOS inputs draw current).
7. Power budget: compute the current of each block and duty cycle; use duty cycling for sensors and radios.
8. Efficient power conversion: use high-efficiency DC-DC converters instead of linear regulators when the voltage drop is large.
9. Use software techniques: efficient algorithms, interrupt-driven rather than polling code.