Delta and adaptive delta modulation

Delta modulation (DM)

Delta modulation is 1-bit DPCM: the signal is oversampled, and only one bit per sample tells whether the signal is above or below the previous staircase approximation, which then moves up or down by a fixed step $\Delta$.

Equations:

$$\begin{aligned} e[n] &= m[n] - m_q[n-1] \\ e_q[n] &= \Delta\,\text{sgn}(e[n]) \quad (\text{bit 1 for } +\Delta,\ 0 \text{ for } -\Delta) \\ m_q[n] &= m_q[n-1] + e_q[n] = \sum_{i=1}^{n} e_q[i] \end{aligned}$$

So the receiver output is the accumulated (integrated) sum of $\pm\Delta$ steps.

DM transmitter

m(t)->[Sampler]->m[n]->(+)--e[n]-->[1-bit    ]--+--> bits
                        ^ -        [quantizer]  |
                        |                       v
                  mq[n-1]                     (+)
                        |                       |
                        +--[Delay z^-1]<--mq[n]-+
                         (accumulator)

DM receiver

bits->[Decoder +/-D]->(+)--+--> mq[n] --> [LPF] --> m(t)
                       ^   |
                       +-[z^-1]  (accumulator)

Noise in DM:

• Slope overload: if the signal slope exceeds $\Delta/T_s$, the staircase cannot follow. No overload needs $\left|\frac{dm}{dt}\right|_{max} \le \Delta f_s$; for a tone, $A_m \le \frac{\Delta f_s}{2\pi f_m}$.
• Granular noise: when the signal is nearly flat, the staircase hunts by $\pm\Delta$.
• SQNR (no overload, single tone): $\text{SQNR} = \frac{3f_s^3}{8\pi^2 f_m^2 W}$.

Adaptive delta modulation (ADM)

In ADM the step size is varied according to the signal slope: large steps for steep parts (to avoid slope overload) and small steps for flat parts (to reduce granular noise).

A common rule (Jayant's algorithm):

$$\Delta[n] = \begin{cases} K\,\Delta[n-1], & b[n] = b[n-1] \\ \Delta[n-1]/K, & b[n] \ne b[n-1] \end{cases} \qquad (K \approx 1.5)$$

with limits $\Delta_{min} \le \Delta[n] \le \Delta_{max}$. Consecutive equal bits mean the staircase is lagging (step grows); alternating bits mean granular hunting (step shrinks).

m(t)->(+)->[1-bit Q]--+--------------> bits
       ^-             |
       |        [Step-size logic]
       |              | D[n]
       |              v
       +--[Accum.]<-[x]
Receiver: same step logic + accumulator + LPF

The receiver uses the same step-size logic on the received bits, so no side information is needed.

Merits and demerits