- 2079 Bhadra (CS II) · 5+5 marks
T1 digital carrier system; adaptive delta modulation
Short answer
T1 multiplexes 24 voice channels sampled at 8 kHz with 8-bit µ-law coding, yielding 1.544 Mb/s. DS1 to DS4 hierarchy: 1.544, 6.312, 44.736, 274.176 Mb/s. ADM varies step size based on successive bits to avoid slope overload and granular noise.
Explain T1 digital carrier system with its multiplexing hierarchy. Explain the principles of Adaptive Delta Modulation (ADM).
T1 digital carrier system
T1 is the North American TDM-PCM carrier that sends 24 voice channels over one twisted-pair line at 1.544 Mb/s.
- Each voice channel is band-limited to 3.4 kHz and sampled at 8 kHz.
- Each sample is µ-law compressed () and coded into 8 bits, giving 64 kb/s per channel.
- One frame = one 8-bit sample from each of the 24 channels + 1 framing bit = 193 bits in 125 µs.
|<--------- one frame = 125 us = 193 bits --------->|
+---+--------+--------+--------+-------+--------+
| F | Ch 1 | Ch 2 | Ch 3 | ... | Ch 24 |
+---+--------+--------+--------+-------+--------+
1 bit 8 bits 8 bits 8 bits 8 bits
F = framing bit (pattern spread over 12 frames)
- Signalling uses robbed bits (the LSB in frames 6 and 12 of a 12-frame superframe).
- The line code is bipolar AMI (B8ZS on newer lines). Repeaters are placed about every 1.8 km.
Multiplexing hierarchy:
24 voice ch x 64 kb/s
|
[ DS1 / T1 ] 1.544 Mb/s 24 ch
| x4
[ DS2 / T2 ] 6.312 Mb/s 96 ch
| x7
[ DS3 / T3 ] 44.736 Mb/s 672 ch
| x6
[ DS4 / T4 ] 274.176 Mb/s 4032 ch
Higher levels add framing and stuffing bits, so DS2 = 6.312 Mb/s rather than Mb/s.
Adaptive Delta Modulation (ADM)
Linear delta modulation (DM) sends 1 bit per sample, which says whether the signal is above or below its staircase approximation. A fixed step size causes two problems:
- Slope overload when the signal changes faster than .
- Granular noise when the signal is nearly flat.
ADM changes the step size to suit the signal slope:
- If several successive output bits are the same (e.g. 1 1 1), the staircase is lagging behind, so the step size is increased. A common rule is to multiply it by 1.5 or 2.
- If the bits alternate (1 0 1 0), the signal is flat, so the step size is decreased (e.g. divided by the same factor), down to a minimum .
m(t) -->(+)--> [Comparator] --+--> output bits b(k)
^- |
| v
| [Step size logic]
| | delta(k)
+--- [Accumulator] <-+
The receiver uses the same logic on the received bits, so no extra side information is sent.
Advantages: much less slope overload and granular noise, a wider dynamic range, and good speech quality at 16–32 kb/s. An example is CVSD (continuously variable slope DM), used in military and Bluetooth voice.
✓ Answer checked by Claude Opus 5.5 (high effort)
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