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Design ROM for X,Y,Z to F1,F2 table

Short answer

8x2 ROM with 3-to-8 decoder. F1 = w0+w1+w5+w7, F2 = w2+w3+w5+w6.

Design a ROM that will store the following words in the corresponding addresses.

XYZF1F2
00010
00110
01001
01101
10000
10111
11001
11110

The table has 3 address inputs, so there are 2^3 = 8 words, each 2 bits wide. The ROM is therefore 8 x 2.

Stored contents

Address (X,Y,Z)Word (F1,F2)
000 (word line 0)10
001 (word line 1)10
010 (word line 2)01
011 (word line 3)01
100 (word line 4)00
101 (word line 5)11
110 (word line 6)01
111 (word line 7)10

Design

Use a 3-to-8 decoder (the address lines select exactly one word line) and one OR gate per output bit. Connect a word line to an OR gate only where that word stores a 1 in that column (a programmable connection at the crosspoint).

OutputWord lines ORed (addresses with a 1)Output expression
F10, 1, 5, 7F1 = w0 + w1 + w5 + w7
F22, 3, 5, 6F2 = w2 + w3 + w5 + w6
 X,Y,Z (address)
    |    +-----------+  w0..w7
    +--->|  3-to-8   |===> word lines ===> [OR] --> F1
         |  decoder  |                     [OR] --> F2
         +-----------+

Each OR input is connected (by a transistor/fuse) to a word line only when that bit of the word is 1; the connection is left open for 0. When an address is applied, the decoder raises one word line and the OR gates output the stored word.

✓ Answer checked by Claude Opus 5.5 (high effort)

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