- Asked 2/19
- 2075 Bhadra · 5 marks
Design ROM for X,Y,Z to F1-F4 table
Short answer
8x4 ROM with 3-to-8 decoder. F1 = w1+w3+w6, F2 = w1+w2+w3+w5, F3 = w0+w3+w4+w6+w7, F4 = w2+w3+w4+w5+w7.
Design a ROM to store the following information:
| X | Y | Z | F1 | F2 | F3 | F4 |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 1 | 1 | 0 | 0 |
| 0 | 1 | 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 1 |
The table has 3 address inputs, so there are 2^3 = 8 words, each 4 bits wide. The ROM is therefore 8 x 4.
Stored contents
| Address (X,Y,Z) | Word (F1,F2,F3,F4) |
|---|---|
| 000 (word line 0) | 0010 |
| 001 (word line 1) | 1100 |
| 010 (word line 2) | 0101 |
| 011 (word line 3) | 1111 |
| 100 (word line 4) | 0011 |
| 101 (word line 5) | 0101 |
| 110 (word line 6) | 1010 |
| 111 (word line 7) | 0011 |
Design
Use a 3-to-8 decoder (the address lines select exactly one word line) and one OR gate per output bit. Connect a word line to an OR gate only where that word stores a 1 in that column (a programmable connection at the crosspoint).
| Output | Word lines ORed (addresses with a 1) | Output expression |
|---|---|---|
| F1 | 1, 3, 6 | F1 = w1 + w3 + w6 |
| F2 | 1, 2, 3, 5 | F2 = w1 + w2 + w3 + w5 |
| F3 | 0, 3, 4, 6, 7 | F3 = w0 + w3 + w4 + w6 + w7 |
| F4 | 2, 3, 4, 5, 7 | F4 = w2 + w3 + w4 + w5 + w7 |
X,Y,Z (address)
| +-----------+ w0..w7
+--->| 3-to-8 |===> word lines ===> [OR] --> F1
| decoder | [OR] --> F2
+-----------+ ...
Each OR input is connected (by a transistor/fuse) to a word line only when that bit of the word is 1; the connection is left open for 0. When an address is applied, the decoder raises one word line and the OR gates output the stored word.
✓ Answer checked by Claude Opus 5.5 (high effort)
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