Largest of four integers processor

Assumption: four 8-bit integers a, b, c, d are available on input ports; the processor outputs the largest value when start is given.

Algorithm

 max = a
 if (b > max) max = b
 if (c > max) max = c
 if (d > max) max = d
 output max

State diagram (FSMD)

 S0 --start--> S1 (MAX=a) --> S2 (if b>MAX: MAX=b)
   ^                                  |
   |                                  v
 S5 (out=MAX, done) <-- S4 (if d>MAX: MAX=d) <-- S3 (if c>MAX: MAX=c)

(gt = comparator output "selected input > MAX".)

Datapath

  a --+
  b --+--> [4:1 mux] --+--> [ > comparator ] --> gt
  c --+     (sel 2b)   |            ^
  d --+                |            |
                       v            |
                   [ MAX register ]-+
                       |
                       v
                      out

Components: a 4:1 multiplexer selecting the input (sel = 00 a, 01 b, 10 c, 11 d), an 8-bit comparator (selected input > MAX), an 8-bit register MAX with load enable (load = gt, or unconditional in S1), and an output buffer. Control signals: sel[1:0], load, out_en.

Controller block diagram

 start, status flags --> +-------------+   +-----------+
 (from datapath)         | Next-state  |-->| State     |
                         | logic       |   | register  |
                         +------^------+   +-----+-----+
                                |   current state |
                                +-----------------+
                                                  v
                                           +-------------+
                                           | Output logic|--> control
                                           +-------------+    signals

6 states, 3-bit state register. Output logic: S1: sel = 00, ld = 1; S2: sel = 01, ld = gt; S3: sel = 10, ld = gt; S4: sel = 11, ld = gt; S5: out_en = 1, done = 1. The controller's inputs are start and the status signal gt from the datapath.