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Three-phase SPWM inverter switching instants
Short answer
In three-phase SPWM, each leg switches when its sinusoidal reference crosses a common triangular carrier. Switching instants are found either by solving the transcendental crossing equation (natural sampling) or by sampling the reference once per carrier period to compute duty cycle d=0.5(1+ma sin ωt_k) (regular sampling). Dead time is added to avoid shoot-through.
Explain the operation of a three phase Sinusoidal PWM inverter with neat circuit diagram and associated waveforms. How switching instants for inverter switch pair of a phase are determined?
A three-phase sinusoidal PWM inverter is a six-switch bridge in which each leg is switched by comparing its own sinusoidal reference (120° apart from the others) with a common triangular carrier. The switching instants are the crossing points of the reference and the carrier.
Circuit
+----+--------+--------+
| | | |
Vdc/2 S1 D1 S3 D3 S5 D5
--- | | | |
O +-a +--b +--c |
--- | | | |
Vdc/2 S4 D4 S6 D6 S2 D2
| | | |
+----+--------+--------+
a, b, c -> 3-phase load
Operation
- References: , , .
- Carrier: triangle of peak , frequency ( odd multiple of 3).
- Leg a: S1 ON, ; S4 ON, .
- Line voltage is a train of pulses of and 0 whose widths vary sinusoidally.
- Fundamental (linear range ): , .
vc /\ /\ /\ /\ /\ /\
/ \/ \/ \/ \/ \/ \
vra .--''''--.
------'----------'----------
vaO _ ___ _____ ___ _
+ _| || | | || |_
- (S1 ON when vra>vc)
How the switching instants of one leg are found
1. Natural sampling (analogue comparison). In one carrier half-period the carrier is a straight line. For a rising slope starting at :
The switching instant is the root of
which is transcendental and is solved numerically (or by an analogue comparator in hardware). At the leg changes state: S1 OFF → S4 ON on the rising slope (as the carrier rises above the reference), and S4 OFF → S1 ON on the falling slope.
2. Regular (uniform) sampling (used in microcontrollers/DSP). The reference is sampled once per carrier period at and held. Then the crossing is found from a straight-line equation:
The ON pulse of S1 is centred in the carrier period (symmetric sampling). For example, at gives : S1 is ON for 90% of that carrier period.
3. Complementary gating with dead time. The pair in a leg (S1–S4) receives complementary signals; a short dead time (both OFF) is inserted at every transition to avoid a shoot-through short circuit. During the load current flows through a diode.
The same procedure applies to legs b and c using , , which gives three balanced pole voltages.
✓ Answer checked by Claude Opus 5.5 (high effort)
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