Space switch and why TST is used

Space (S) switch in a digital switching system

A digital space switch is a time-multiplexed space switch (TMS). It connects $N$ incoming PCM highways to $M$ outgoing highways. Its crosspoints are electronic gates, and the connection pattern changes every time slot under the control of control memories. It changes the highway of a sample but keeps its time slot.

Block diagram

 Incoming          Crosspoint           Outgoing
 highways          matrix               highways
 HW1 ------->+--------------------+---> OHW1
 HW2 ------->|   N x M gates      |---> OHW2
  ...        |   (or M x N:1 MUX) |      ...
 HWN ------->+--------------------+---> OHWM
                ^    ^        ^
             [CM1] [CM2] ... [CMM]   c words each
                ^
         time-slot counter <--- clock (frame sync)
                ^
         call-control processor (writes CMs)

Logical diagram (one output column)

Each output is in effect an $N$-to-1 multiplexer whose select lines come from its control memory.

  I1 --|AND|--+
  I2 --|AND|--+
   ...        +--[OR]--> output Oj
  IN --|AND|--+
        ^
   decoder (log2 N -> N lines)
        ^
   CMj word for current slot

Only the AND gate selected by the decoder is enabled in a slot, so only that input reaches the output.

Working principle

1. Each control memory has $c$ words, one per slot; word $t$ of CM$_j$ holds the address of the input highway to connect to output $j$ in slot $t$.
2. The time-slot counter, synchronised to the frame, steps $t = 0 \dots c-1$.
3. In slot $t$, every CM is read; each decoder enables one gate, so input $I_a$ is connected to output $O_j$ for the duration of slot $t$ (about 3.9 µs for a 32-slot frame).
4. In the next slot different gates may be enabled, so each crosspoint is shared by up to $c$ calls.
5. At call set-up the processor writes the input number into the right CM word; at release it clears it.

Example: CM$_2$ word 5 = 3 → in slot 5, I3 is connected to O2. Word 6 = 1 → in slot 6, I1 is connected to O2.

Control memory size: $M \times c \times \lceil\log_2 N\rceil$ bits (or with one-hot words, $N$ bits each).

Why TST and not TS or ST

Problem of two-stage TS and ST:

• TS: the TSI moves the sample to the output slot $j$, then the S stage must connect the highways in slot $j$. If slot $j$ on the output highway is already taken by a call from another input highway, the call is blocked.
• ST: the S stage must connect the highways in the input slot $i$; if slot $i$ is already busy into that output highway, the call is blocked.
• Only one path exists, so blocking is about equal to link occupancy $p$ (e.g. 0.3 to 0.7), far above an acceptable grade of service (e.g. 0.002).

TST gives many paths: the input TSI can move the sample to any free internal slot $x$, the S stage switches in slot $x$, and the output TSI moves it to slot $j$. There are $l$ paths:

$$P_B = \left[1 - (1 - p')^2\right]^{l}, \quad p' = \frac{pc}{l}$$

For example, $c = l = 32$, $p = 0.5$: $P_B = 0.75^{32} \approx 1.0 \times 10^{-4}$.

Why TST rather than STS:

1. Paths in TST come from time slots; increasing $l$ (time expansion) needs only faster memory and logic, which is cheap.
2. In STS, more paths need more centre TSIs and more crosspoints (space expansion), which is costly.
3. Non-blocking needs only $l \ge 2c - 1$, easily met (e.g. 64 internal slots for 32-slot links).
4. The space stage is small ($N \times N$ highways), and the time stages are just memories, so TST is cheaper, more modular and suits large exchanges.
5. Path search is simple: find one internal slot free on two links; the reverse path can use slot $x + l/2$.

Hence practical digital exchanges use TST (or its extension TSST) instead of two-stage TS or ST switches.