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Block diagram model of R-L-C-L-R circuit

Short answer

Define V1 across C, I1 in R1–L1, I2 in L2–R2. Block diagram: I1=(Vi-V1)/(R1+sL1), V1=(I1-I2)/(sC), I2=V1/(R2+sL2), Vo=R2 I2. Reduction yields Vo/Vi = R2 / [CL1L2 s^3 + C(L1R2+L2R1)s^2 + (CR1R2+L1+L2)s + R1+R2].

Develop block diagram model for the circuit shown in figure below. [Figure: input Vi; series R1 and L1 to a node; capacitor C from that node to ground; series L2 to the output node; R2 from output node to ground; Vo across R2]

Let V1V_1 = voltage across CC, I1I_1 = current in R1R_1–L1L_1, I2I_2 = current in L2L_2–R2R_2.

Element equations (Laplace)

I1(s)=Vi(s)−V1(s)R1+sL1V1(s)=1sC[I1(s)−I2(s)]I2(s)=V1(s)R2+sL2Vo(s)=R2 I2(s)\begin{aligned} I_1(s) &= \frac{V_i(s) - V_1(s)}{R_1 + sL_1} \\ V_1(s) &= \frac{1}{sC}\left[I_1(s) - I_2(s)\right] \\ I_2(s) &= \frac{V_1(s)}{R_2 + sL_2} \\ V_o(s) &= R_2\,I_2(s) \end{aligned}

Block diagram

Here Z1=R1+sL1Z_1 = R_1 + sL_1 and Z2=R2+sL2Z_2 = R_2 + sL_2.

 Vi─►(Σ)►[1/Z1]─►(Σ)►[1/sC]─┬─►[1/Z2]─┬─►[R2]─►Vo
      ▲-          ▲-        │          │
      │           └── I2 ───┼──────────┘
      └── V1 ───────────────┘

Reduction

Inner loop (between I1I_1 and V1V_1, feedback via 1R2+sL2\frac{1}{R_2+sL_2}):

V1I1=1sC1+1sC(R2+sL2)=R2+sL2sC(R2+sL2)+1\frac{V_1}{I_1} = \frac{\frac{1}{sC}}{1 + \frac{1}{sC(R_2+sL_2)}} = \frac{R_2 + sL_2}{sC(R_2+sL_2) + 1}

Outer loop with forward 1R1+sL1\frac{1}{R_1+sL_1} and unity feedback of V1V_1, then multiply by R2R2+sL2\frac{R_2}{R_2+sL_2}:

Vo(s)Vi(s)=R2(R1+sL1)+(R2+sL2)+sC(R1+sL1)(R2+sL2)\frac{V_o(s)}{V_i(s)} = \frac{R_2}{(R_1 + sL_1) + (R_2 + sL_2) + sC(R_1 + sL_1)(R_2 + sL_2)}

Expanded:

Vo(s)Vi(s)=R2CL1L2s3+C(L1R2+L2R1)s2+(CR1R2+L1+L2)s+R1+R2\frac{V_o(s)}{V_i(s)} = \frac{R_2}{CL_1L_2s^3 + C(L_1R_2 + L_2R_1)s^2 + (CR_1R_2 + L_1 + L_2)s + R_1 + R_2}

✓ Answer checked by Claude Opus 5.5 (high effort)

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