- 2075 Asoj · 3+3 marks
BCD decoder; 1's and 2's complements
Short answer
BCD decoder activates one of ten outputs: D0=A'B'C'D', D1=A'B'C'D, D2=B'CD', D3=B'CD, D4=BC'D', D5=BC'D, D6=BCD', D7=BCD, D8=AD', D9=AD. 1's complement inverts all bits; 2's complement adds 1 to the 1's complement.
Realize the circuit diagram for BCD decoder. Explain 1's and 2's complements with examples?
BCD decoder (BCD-to-decimal, 4-to-10)
A BCD decoder takes a 4-bit BCD code ( = MSB) and activates one of ten outputs – (IC 7442). Codes 1010–1111 never occur, so they are don't-cares and allow partial decoding.
| Digit | ABCD | Full decoding | Simplified (with don't-cares) |
|---|---|---|---|
| 0 | 0000 | ||
| 1 | 0001 | ||
| 2 | 0010 | ||
| 3 | 0011 | ||
| 4 | 0100 | ||
| 5 | 0101 | ||
| 6 | 0110 | ||
| 7 | 0111 | ||
| 8 | 1000 | ||
| 9 | 1001 |
A B C D A' B' C' D' (inverters)
| | | |
+--+--+--+--[AND]--- D0 = A'B'C'D'
+--+--+--+--[AND]--- D1 = A'B'C'D
... (one AND gate per output)
+--------+--[AND]--- D8 = AD'
+--------+--[AND]--- D9 = AD
Ten AND gates and four inverters form the decoder.
1's and 2's complements
1's complement: invert every bit (0 → 1, 1 → 0). Example: 1's complement of is .
2's complement: 1's complement + 1. Example: 2's complement of is .
They represent negative numbers and turn subtraction into addition. Example in 4 bits:
1's complement method 2's complement method
1001 (9) 1001 (9)
+ 1010 (1's comp of 0101) + 1011 (2's comp of 0101)
------ ------
1 0011 1 0100
+1 end-around carry carry discarded
------
0100 = 4 0100 = 4
In 1's complement the end carry is added back; in 2's complement it is discarded. 2's complement has a single zero and is used in computers.
✓ Answer checked by Claude Opus 5.5 (high effort)
Related questions
- Combinational vs sequential; BCD-to-decimal decoder · Digital Logic, chapter 4
- BCD-to-seven-segment decoder, segments a and e · Digital Logic, chapter 4
- BCD-to-7-segment decoder; frequency counter · Digital Logic, chapter 11
- K-map Σ(0,1,4,8,10,11,12)+d, realize circuit · Digital Logic, chapter 3 · asked 2×
- Full subtractor using decoder; combinational circuit · Digital Logic, chapter 4
- DEMUX vs decoder; seven-segment "b" segment · Digital Logic, chapter 4
- Stereo FM encoder and decoder block diagram · Communication Systems, chapter 3
- Q and center frequency; realize −2000/(s²+500s+10⁶) · Filter Design, chapter 6
- Tow-Thomas LPF derivation; realize −2000/(s²+500s+10⁶) · Filter Design, chapter 6
- Hamiltonian path and circuit with diagram · Discrete Structure, chapter 4