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DEMUX vs decoder; seven-segment "b" segment

Short answer

A demultiplexer routes one data input to a selected output, while a decoder activates one output line for a given code. Segment b expression: b = B' + (C XNOR D). Realize with an inverter, an XNOR gate, and an OR gate.

Compare a demultiplexer with the decoder. What is a seven-segment decoder? Find out the simplest logic expression for "b" segment of the BCD to 7-segment display decoder and realize the circuit.

DEMUX vs decoder

A demultiplexer sends one data input to one of 2n2^n outputs chosen by nn select lines. A decoder converts an nn-bit input code into one active line out of 2n2^n lines. A decoder with an enable input works as a DEMUX if the enable is used as the data input.

PointDemultiplexerDecoder
Inputs1 data + n selectn code inputs (+ enable)
FunctionRoutes data to a chosen lineActivates the line for a code
Output contentCopy of the data bitFixed 1 (or 0) on one line
UseData distribution, serial-to-parallelAddress decoding, code conversion
Example1:8 DEMUX3-to-8 decoder (74138)

Seven-segment decoder

A BCD-to-seven-segment decoder (e.g. 7447/7448) takes a 4-bit BCD digit ABCDABCD and produces seven outputs aa to gg that light the segments of an LED display so that the decimal digit 0–9 is shown. Inputs 1010–1111 never occur, so they are don't-cares.

     a
    ---
 f | g | b
    ---
 e |   | c
    ---
     d

Simplest expression for segment "b"

Segment b is ON for digits 0, 1, 2, 3, 4, 7, 8, 9 and OFF for 5 and 6 (standard 7447 style).

b=Σm(0,1,2,3,4,7,8,9)+d(10,11,12,13,14,15)b = \Sigma m(0,1,2,3,4,7,8,9) + d(10,11,12,13,14,15)

K-map (rows AB, columns CD):

AB \ CD00011110
001111
011010
11XXXX
1011XX

Groups: rows 00 and 10 (all B=0B=0) give B′B'; column 00 gives C′D′C'D'; column 11 gives CDCD.

b=B′+C′D′+CD=B′+(C⊙D)b = B' + C'D' + CD = B' + (C \odot D)

Circuit

 B ---[NOT]--- B' ---------+
                           +--[OR]--- b
 C --+                     |
     +--[XNOR]--- C⊙D -----+
 D --+

So segment b needs one inverter, one XNOR and one 2-input OR gate (or with AND/OR: C′D′C'D' and CDCD from two AND gates and a 3-input OR).

✓ Answer checked by Claude Opus 5.5 (high effort)

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